IP Library › Granted Patent US 10,504,914
Granted Patent B2
US 10,504,914 · App. 15/990,696 · Granted Dec 10, 2019

Integrated circuit structure and manufacturing method thereof

Inventor: Zih-Song Wang (Nantou County, TW)
Assignee: Powerchip Semiconductor Manufacturing Corporation
H01L27/11578H01L21/762H01L27/1157H01L29/0649H01L29/1087
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Quick Facts
Patent No.
US 10,504,914
App. No.
15/990,696
Filed
May 28, 2018
Granted
Dec 10, 2019
Kind
B2
Art Unit
2816
USPC
257/374
Abstract

An integrated circuit structure including a substrate, a stacked structure, and first contacts is provided. The stacked structure is disposed on the substrate and includes first dielectric layers and conductive layers alternately stacked. The stacked structure has openings passing through the conductive layers. The first contacts are located in the openings. Bottoms of the first contacts are located at different heights. The first contacts and the conductive layers are electrically connected in a one-to-one manner. The first contacts and the conductive layers that are not electrically connected to each other are isolated from each other.

Claims (14)

1. An integrated circuit structure, comprising:

a substrate;

a stacked structure, disposed on the substrate and comprising first dielectric layers and conductive layers alternately stacked, wherein the stacked structure has openings passing through the conductive layers;

first contacts, located in the openings, wherein bottoms of the first contacts are located at different heights, the first contacts and the conductive layers are electrically connected in a one-to-one manner, the first contacts and the conductive layers which are not electrically connected to each other are isolated from each other, and the first contacts are not electrically connected to an uppermost layer in the conductive layers;

second dielectric layers, disposed in the openings, wherein the first contacts are located on the second dielectric layers;

third dielectric layers, disposed in the openings and located between the conductive layers and the first contacts, wherein bottoms of the third dielectric layers are located at different heights; and

second contacts, electrically connected to the uppermost layer in the conductive layers and the first contacts respectively.

2. The integrated circuit structure according to claim 1 , wherein a material of the conductive layers comprises doped polycrystalline silicon or metal.

3. The integrated circuit structure according to claim 1 , wherein an arrangement of the first contacts comprises a two-dimensional arrangement or a one-dimensional arrangement.

4. The integrated circuit structure according to claim 1 , further comprising:

isolation layers, wherein each of the isolation layers is disposed between two adjacent first dielectric layers, and a portion of the isolation layers is located between the conductive layers and the third dielectric layers.

5. The integrated circuit structure according to claim 1 , wherein each of the third dielectric layers is further extended between two adjacent first dielectric layers.

6. The integrated circuit structure according to claim 1 , further comprising:

a fourth dielectric layer covering the stacked structure and the first contacts, and the second contacts being located in the fourth dielectric layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 050659/0432 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2018
From: WANG, ZIH-SONG
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 045908/0845 →
Priority Claims (1)
TW 107105691 A · Feb 21, 2018 · national
Continuity (1)
Related Publication 20190259773A1 · Aug 22, 2019
Cited By (4)
US 12,302,563 US 12,347,778 US 12,610,547 US 12,701,712