IP Library › Granted Patent US 10,718,986
Granted Patent B2
US 10,718,986 · App. 15/991,170 · Granted Jul 21, 2020

Display device

Inventors: Hajime Kimura (Atsugi, JP); Atsushi Umezaki (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G02F1/1368G02F1/13624G02F1/136259G02F1/136286G09G3/006G09G3/3648H01L27/124H01L27/1225H01L27/1255H01L29/7869G02F1/1339G02F1/13439G02F1/133345G02F1/134309G02F1/167G02F2001/133302G02F2001/136254G09G2230/00G09G2310/0251H01L29/42384
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Quick Facts
Patent No.
US 10,718,986
App. No.
15/991,170
Granted
Jul 21, 2020
Kind
B2
Abstract

An object is to provide a display device that performs accurate display. A circuit is formed using a transistor that includes an oxide semiconductor and has a low off-state current. A precharge circuit or an inspection circuit is formed in addition to a pixel circuit. The off-state current is low because the oxide semiconductor is used. Thus, it is not likely that a signal or voltage is leaked in the precharge circuit or the inspection circuit to cause defective display. As a result, a display device that performs accurate display can be provided.

Claims (66)

1. A display device comprising:

a pixel portion including a plurality of pixels; and

an inspection circuit configured to inspect whether a second transistor is operating normally or not,

wherein the inspection circuit includes a plurality of first transistors,

wherein each of the plurality of pixels includes the second transistor and a display element,

wherein each of the plurality of first transistors and the second transistor includes an oxide semiconductor, and

wherein an off-state current per channel width of 1 μm of each of the plurality of first transistors and the second transistor is 10 zA/μm or less.

2. The display device according to claim 1 , wherein the oxide semiconductor included in the plurality of first transistors and the second transistor is an intrinsic semiconductor.

3. The display device according to claim 1 , wherein the display device is a liquid crystal display device.

4. An electronic device comprising:

the display device according to claim 1 ; and

an operation switch.

5. The display device according to claim 1 , wherein the inspection whether the second transistor is operating normally or not is performed during manufacturing the display device.

6. A display device comprising:

a pixel portion including a plurality of pixels; and

an inspection circuit,

wherein the inspection circuit includes a plurality of first transistors,

wherein each of the plurality of pixels includes a second transistor and a display element,

wherein gates of the plurality of first transistors are electrically connected to each other,

wherein first terminals of the plurality of first transistors are electrically connected to each other,

wherein all of second terminals of the plurality of first transistors are electrically connected to the pixel portion,

wherein the gates of the plurality of first transistors are in a floating state,

wherein each of the plurality of first transistors and the second transistor includes an oxide semiconductor, and

wherein an off-state current per channel width of 1 μm of each of the plurality of first transistors and the second transistor is 10 zA/μm or less.

7. The display device according to claim 6 , wherein the oxide semiconductor included in the plurality of first transistors and the second transistor is an intrinsic semiconductor.

8. The display device according to claim 6 , wherein the display device is a liquid crystal display device.

9. An electronic device comprising:

the display device according to claim 6 ; and

an operation switch.

10. A display device comprising:

a pixel portion including a plurality of pixels; and

an inspection circuit,

wherein the inspection circuit includes a plurality of first transistors,

wherein each of the plurality of pixels includes a second transistor and a display element,

wherein gates of the plurality of first transistors are electrically connected to each other,

wherein first terminals of the plurality of first transistors are electrically connected to each other,

wherein all of second terminals of the plurality of first transistors are electrically connected to the pixel portion,

wherein the first terminals of the plurality of first transistors are in a floating state,

wherein each of the plurality of first transistors and the second transistor includes an oxide semiconductor, and

wherein an off-state current per channel width of 1 μm of each of the plurality of first transistors and the second transistor is 10 zA/μm or less.

11. The display device according to claim 10 , wherein the oxide semiconductor included in the plurality of first transistors and the second transistor is an intrinsic semiconductor.

12. The display device according to claim 10 , wherein the display device is a liquid crystal display device.

13. An electronic device comprising:

the display device according to claim 10 ; and

an operation switch.

14. A display device comprising:

a pixel portion including a plurality of pixels; and

an inspection circuit configured to inspect whether a second transistor is operating normally or not,

wherein the inspection circuit includes a plurality of first transistors,

wherein each of the plurality of pixels includes the second transistor and a display element,

wherein each of the plurality of first transistors and the second transistor includes an intrinsic oxide semiconductor, and

wherein at least one of a gate or a first terminal of the plurality of first transistors is in a floating state.

15. The display device according to claim 14 , wherein the display device is a liquid crystal display device.

16. An electronic device comprising:

the display device according to claim 14 ; and

an operation switch.

17. The display device according to claim 14 ,

wherein gates of the plurality of first transistors are electrically connected to each other,

wherein first terminals of the plurality of first transistors are electrically connected to each other,

wherein all of second terminals of the plurality of first transistors are electrically connected to the pixel portion, and

wherein the gates of the plurality of first transistors are in a floating state.

18. The display device according to claim 14 ,

wherein gates of the plurality of first transistors are electrically connected to each other,

wherein first terminals of the plurality of first transistors are electrically connected to each other,

wherein all of second terminals of the plurality of first transistors are electrically connected to the pixel portion, and

wherein the first terminals of the plurality of first transistors are in a floating state.

Priority Claims (1)
JP 2010-028285 · Feb 11, 2010 · national
Continuity (5)
Continuation 15711029 · Sep 21, 2017
Division 15262611 · Sep 12, 2016
Continuation 14602876 · Jan 22, 2015
Continuation 13021955 · Feb 7, 2011
Related Publication 20180275439A1 · Sep 27, 2018
Cited By (2)
US 12,374,284 US 12,416,838