IP Library Granted Patent US 10,510,824
Granted Patent B2
US 10,510,824 · App. 15/992,645 · Granted Dec 17, 2019

Semiconductor device having resistance elements and fabrication method thereof

Inventors: Taiji Ema (Inabe, JP); Nobuhiro Misawa (Kuwana, JP); Kazuyuki Kumeno (Kuwana, JP); Makoto Yasuda (Kuwana, JP)
Assignee: Mie Fujitsu Semiconductor Limited
H01L28/20H01L27/0802H01L27/0629
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Quick Facts
Patent No.
US 10,510,824
App. No.
15/992,645
Granted
Dec 17, 2019
Kind
B2
Abstract

A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration C X . The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration C Y lower than the concentration C X . A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration C X . A sign of a TCR of the second polycrystalline silicon changes at the concentration C Y .

Claims (17)

1. A semiconductor device comprising:

a first polycrystalline silicon having a negative temperature coefficient and having a first width; and

a second polycrystalline silicon having a positive temperature coefficient and having a second width larger than the first width, wherein:

the first polycrystalline silicon contains first impurities at a first concentration throughout a direction perpendicular to a direction of the first width, in a plan view; and

the second polycrystalline silicon contains the first impurities at the first concentration throughout a direction perpendicular to a direction of the second width, in the plan view.

2. The semiconductor device according to claim 1 , wherein the first concentration and the second concentration are higher than or equal to 1×10 20 cm −3 and lower than or equal to 1×10 21 cm −3 .

3. The semiconductor device according to claim 1 , wherein the first polycrystalline silicon and the second polycrystalline silicon are electrically connected in series.

4. The semiconductor device according to claim 1 , wherein the first impurities are p-type impurities.

5. The semiconductor device according to claim 1 , wherein the first polycrystalline silicon and the second polycrystalline silicon are electrically connected in parallel.

6. The semiconductor device according to claim 1 , wherein one end portion of the first polycrystalline silicon and one end portion of the second polycrystalline silicon are electrically connected in series.

7. The semiconductor device according to claim 1 , wherein:

one end portion of the first polycrystalline silicon and one end portion of the second polycrystalline silicon are electrically connected;

the other end portion of the first polycrystalline silicon and the other end portion of the second polycrystalline silicon are electrically connected; and

the first polycrystalline silicon and the second polycrystalline silicon are electrically connected in parallel.

8. The semiconductor device according to claim 1 , wherein the first polycrystalline silicon and the second polycrystalline silicon are formed as continuous one body and electrically connected.

9. The semiconductor device according to claim 8 , wherein the first polycrystalline silicon and the second polycrystalline silicon are electrically connected in series.

10. The semiconductor device according to claim 1 , wherein a first sheet resistance of the first polycrystalline silicon is higher than a second sheet resistance of the second polycrystalline silicon.

Priority Claims (1)
JP 2016-029457 · Feb 19, 2016 · national
Continuity (2)
Division 15402367 · Jan 10, 2017
Related Publication 20180277618A1 · Sep 27, 2018