Decoupling capacitor circuit
A decoupling capacitor includes a first p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library, a first n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in the standard cell library, a second PMOS transistor connected between the first NMOS transistor and the power rail, and a second NMOS transistor connected between the first PMOS transistor and the ground rail, wherein a gate of the second PMOS transistor is connected to a gate of the second NMOS transistor.
1. A decoupling capacitor, comprising:
a first p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library;
a first n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in the standard cell library;
a second PMOS transistor connected between the first NMOS transistor and the power rail; and
a second NMOS transistor connected between the first PMOS transistor and the ground rail,
wherein a gate of the second PMOS transistor is connected to a gate of the second NMOS transistor,
wherein a drain of the second NMOS transistor is connected to a gate of the first PMOS transistor, and a source of the second NMOS transistor is connected to the ground rail, and
wherein a drain of the second PMOS transistor is directly connected to a gate of the first NMOS transistor.
2. The decoupling capacitor of claim 1 , wherein a source and a drain of the first PMOS transistor are connected to the power rail, along with an N-well region of the first PMOS transistor.
3. The decoupling capacitor of claim 1 , wherein a source and a drain of the first NMOS transistor are connected to the ground rail, along with a bulk region of the first NMOS transistor.
4. The decoupling capacitor of claim 1 , wherein a source of the second PMOS transistor is connected to the power rail.
5. The decoupling capacitor of claim 4 , wherein the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor have dimensions determined such that in response to a supply voltage being applied from the power rail, a voltage level at the gate of the second PMOS transistor has a level that is 40 to 60 percent of a voltage level of the supply voltage.
6. The decoupling capacitor of claim 1 , wherein the first PMOS transistor and the second PMOS transistor are formed in a P-type active region.
7. The decoupling capacitor of claim 1 , wherein the drain region of the first PMOS transistor is connected to the power rail by a metal wiring layer through a contact.
8. The decoupling capacitor of claim 1 wherein the first PMOS transistor and the second PMOS transistor share a first shared source region.
9. The decoupling capacitor of claim 8 , wherein the first shared source region is connected to the power rail by a metal wiring layer through a contact.
10. The decoupling capacitor of claim 1 , wherein the first NMOS transistor and the second NMOS transistor are formed in an N-type active region.
11. The decoupling capacitor of claim 1 , wherein the drain region of the first NMOS transistor is connected to the ground rail by a metal wiring layer through a contact.
12. The decoupling capacitor of claim 1 , wherein the first NMOS transistor and the second NMOS transistor share a second shared source region.
13. The decoupling capacitor of claim 12 , wherein the second shared source region is connected to the ground rail by a metal wiring layer through a contact.
14. A decoupling capacitor, comprising:
a first p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library;
a first n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in the standard cell library;
a second PMOS transistor connected between the first NMOS transistor and the power rail; and
a second NMOS transistor connected between the first PMOS transistor and the ground rail,
wherein a gate of the second PMOS transistor is connected to a gate of the second NMOS transistor, and
wherein the first NMOS transistor and the second NMOS transistor share a shared source region.
15. A decoupling capacitor, comprising:
a first p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library;
a first n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in the standard cell library;
a second PMOS transistor connected between the first NMOS transistor and the power rail; and
a second NMOS transistor connected between the first PMOS transistor and the ground rail,
wherein a gate of the second PMOS transistor is connected to a gate of the second NMOS transistor,
wherein the first PMOS transistor and the second PMOS transistor share a shared source region.