Integrated circuit memory devices having impurity-doped dielectric regions therein and methods of forming same

1. A semiconductor device, comprising:

a blocking dielectric disposed on a lower region;

a stack structure comprising an interlayer insulating layer and a gate electrode facing the blocking dielectric;

a lateral impurity region disposed within a boundary region between the interlayer insulating layer and the blocking dielectric; and

a lower impurity region disposed within a boundary region between the lower region and the blocking dielectric.

2. The semiconductor device of claim 1 , wherein the lower region comprises a silicon region or a semiconductor region, and the blocking dielectric contacts the silicon region or the semiconductor region.

3. The semiconductor device of claim 1 , further comprising:

a channel semiconductor layer contacting the lower region, and facing the blocking dielectric;

a data storage layer disposed between the channel semiconductor layer and the blocking dielectric, and spaced apart from the lower region; and

a tunnel dielectric disposed between the data storage layer and the channel semiconductor layer, and spaced apart from the lower region.

4. The semiconductor device of claim 3 , further comprising:

a gate dielectric disposed between the gate electrode and the interlayer insulating layer, and extending between the gate electrode and the blocking dielectric to contact the blocking dielectric; and

wherein the gate dielectric is formed of a high-k dielectric having a dielectric constant higher than a dielectric constant of the blocking dielectric.

5. The semiconductor device of claim 4 , wherein the lateral impurity region extends into a boundary region between the gate dielectric and the blocking dielectric.

6. The semiconductor device of claim 1 , wherein the lateral impurity region and the lower impurity region comprise the same impurity, and the same impurity comprises carbon.

7. A semiconductor device comprising:

memory cell vertical structures disposed on a substrate, each of the memory cell vertical structures comprising a first gate dielectric;

a stack structure disposed on the substrate, and comprising an interlayer insulating layer and a gate electrode facing the memory cell vertical structures; and

a lateral impurity region disposed within a boundary region between the memory cell vertical structures and the stack structure.

8. The semiconductor device of claim 7 , further comprising a second gate dielectric disposed between the interlayer insulating layer and the gate electrode, and extending between the gate electrode and the first gate dielectric.

9. The semiconductor device of claim 8 , wherein the first gate dielectric comprises a blocking dielectric contacting the interlayer insulating layer and the second gate dielectric; and wherein the lateral impurity region is disposed within a boundary region between the blocking dielectric and the interlayer insulating layer, and within a boundary region between the blocking dielectric and the second gate dielectric.

10. The semiconductor device of claim 9 , wherein the first gate dielectric further comprises an data storage layer and a tunnel dielectric; wherein the data storage layer is disposed between the blocking dielectric and the tunnel dielectric; wherein the blocking dielectric has a first surface facing the stack structure, and a second surface facing the data storage layer, and wherein the lateral impurity region is closer to the first surface of the blocking dielectric than to the second surface of the blocking dielectric.

11. The semiconductor device of claim 7 , wherein an impurity of the lateral impurity region comprises carbon.

12. The semiconductor device of claim 7 , further comprising:

separation structures disposed on the substrate;

wherein the separation structures pass through the stack structure;

wherein the memory cell vertical structures are disposed between the separation structures;

wherein the interlayer insulating layer and the gate electrode are provided as a plurality of interlayer insulating layers and a plurality of gate electrodes, respectively, and the plurality of interlayer insulating layers and the plurality of gate electrodes are alternately and repeatedly stacked, and

wherein the stack structure includes the plurality of interlayer insulating layers and the plurality of gate electrodes.

13. The semiconductor device of claim 12 , wherein a distance between some of the plurality of interlayer insulating layers of the stack structure disposed in a region close to the separation structures, and adjacent to each other in a vertical direction, is greater than a distance between the others of the plurality of interlayer insulating layers disposed in a region distant from the separation structures, and adjacent to each other in the vertical direction.

14. A semiconductor device comprising:

a lower region;

a blocking dielectric disposed on the lower region;

a stack structure comprising an interlayer insulating layer and a gate electrode facing the blocking dielectric; and

a lower impurity region disposed within a boundary region between the lower region and the blocking dielectric.

15. The semiconductor device of claim 14 , wherein the lower region comprises a semiconductor region or a silicon region.

16. The semiconductor device of claim 14 , wherein the blocking dielectric comprises an upper portion contacting the stack structure, and a lower portion contacting the lower region.

17. The semiconductor device of claim 16 , further comprising a lateral impurity region disposed within a boundary region between the stack structure and the blocking dielectric.

18. The semiconductor device of claim 17 , wherein the lateral impurity region and the lower impurity region comprise carbon as impurities.

19. The semiconductor device of claim 14 , further comprising:

a channel semiconductor layer contacting the lower region;

an data storage layer disposed between the channel semiconductor layer and the blocking dielectric, and spaced apart from the lower region; and

a tunnel dielectric disposed between the data storage layer and the channel semiconductor layer, and spaced apart from the lower region.

20. The semiconductor device of claim 19 , further comprising:

a pad layer disposed on the channel semiconductor layer, and electrically connected to the channel semiconductor layer;

a bit line contact plug electrically connected to the pad layer; and

a bit line electrically connected to the bit line contact plug.