IP Library Granted Patent US 10,312,090
Granted Patent B2
US 10,312,090 · App. 16/003,058 · Granted Jun 4, 2019

Patterning method

Inventors: Feng-Yi Chang (Tainan, TW); Fu-Che Lee (Taichung, TW); Chieh-Te Chen (Kaohsiung, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L21/0338H01L21/0332H01L21/0335H01L21/0337H01L27/10894
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Quick Facts
Patent No.
US 10,312,090
App. No.
16/003,058
Granted
Jun 4, 2019
Kind
B2
Abstract

A patterning method is disclosed. A substrate having a hard mask layer and a first material layer formed thereon is provided. The first material layer is patterned into first array patterns and first peripheral patterns. The first array patterns are further transferred into first spacer patterns. Subsequently, a planarization layer and a second material layer are successively formed on the substrate. The second material layer is patterned into second array patterns and second peripheral patterns. The second array patterns are further transferred into second spacer patterns. The second spacer patterns partially overlap the first spacer patterns. The second peripheral patterns do not overlap the first peripheral pattern. The first spacer patterns not overlapped by the second spacer patterns are removed to obtain third array patterns. The hard mask layer is then etched using the third array patterns, the second peripheral patterns and the first peripheral patterns as an etching mask.

Claims (35)

1. A patterning method, comprising:

providing a substrate having a hard mask layer formed thereon, wherein an array region and peripheral region are defined on the substrate;

forming a first material layer on the hard mask layer;

patterning the first material layer to form first array patterns in the array region and first peripheral patterns in the peripheral region;

performing a first self-aligned reverse patterning (SARP) process to transfer the first array pattern into first spacer patterns;

forming a planarization layer completely covering the first spacer patterns and the first peripheral patterns;

forming a second material layer on the planarization layer;

patterning the second material layer to form second array patterns in the array region and second peripheral patterns in the peripheral region;

performing a second self-aligned reverse patterning (SARP) process to transfer the second array pattern into second spacer patterns, wherein the second spacer patterns partially vertically overlap the first spacer patterns, wherein the second peripheral patterns do not vertically overlap the first peripheral pattern;

using the second spacer patterns and the second peripheral patterns as an etching mask to etch the planarization layer until portions of the first spacer patterns not overlapped by the second spacer patterns and the first peripheral patterns are exposed;

removing the exposed portions of the first spacer patterns to form third array patterns; and

using the third array patterns, the second peripheral patterns and the first peripheral patterns as an etching mask to etch the hard mask layer thereby forming a patterned hard mask layer.

2. The patterning method according to claim 1 , wherein the first array patterns are straight-line shaped features extending along a first direction, the second array patterns are straight-line shaped features and extending along a second direction.

3. The patterning method according to claim 2 , wherein the first direction and the second direction are perpendicular.

4. The patterning method according to claim 2 , wherein the first direction and the second direction define an included angle smaller than 90 degrees.

5. The patterning method according to claim 2 , wherein the first peripheral patterns and the second peripheral patterns extend along the same direction that is either the first direction or the second direction.

6. The patterning method according to claim 5 , wherein the first peripheral patterns and the second peripheral patterns are alternately arranged.

7. The patterning method according to claim 2 , wherein the first SARP process comprising:

forming a first covering layer covering the first peripheral patterns;

forming a first spacer material layer conformally covering the first array patterns and the first covering layer;

etching the first spacer material layer to form first spacer patterns on sidewalls of the first array patterns; and

removing the first array patterns and the first covering layer.

8. The patterning method according to claim 2 , wherein the second SARP process comprising:

forming a second covering layer covering the second peripheral patterns;

forming a second spacer material layer conformally covering the second array patterns and the second covering layer;

etching the second spacer material layer to form second spacer patterns on sidewalls of the second array patterns; and

removing the second array patterns and the second covering layer.

9. The patterning method according to claim 1 , wherein the second spacer patterns are also removed when removing the exposed portions of the first spacer patterns.

10. The patterning method according to claim 1 , wherein the third array patterns are island shaped features.

11. The patterning method according to claim 1 , wherein the first material layer and the second material layer are made of a same material, and the first spacer patterns and the second spacer patterns are made of a same material that is different from that of the first material layer and the second material layer.

12. The patterning method according to claim 11 , wherein the first material layer and the second material layer are made of polysilicon, and the first spacer patterns and the second spacer patterns are made of silicon oxide.

13. The patterning method according to claim 1 , wherein the planarization layer is an organic dielectric layer.

14. The patterning method according to claim 1 , wherein the hard mask layer is made of silicon nitride.

15. The patterning method according to claim 1 , further comprising using the patterned hard mask layer as an etching mask to etch a target layer on the substrate.

16. The patterning method according to claim 15 , wherein the target layer is made of metal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: CHANG, FENG-YI; LEE, FU-CHE; CHEN, CHIEH-TE
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 046021/0840 →
Priority Claims (1)
CN 2017 1 0628501 · Jul 28, 2017 · national
Continuity (1)
Related Publication 20190035631A1 · Jan 31, 2019
Cited By (3)
US 12,396,369 US 12,451,362 US 12,628,596