Device testing architecture, method, and system
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
1. An integrated circuit comprising:
(a) a core of functional circuits having functional inputs and outputs, the core including a core wrapper that includes:
i. core wrapper parallel inputs,
ii. core wrapper parallel outputs,
iii. a core wrapper serial input,
iv. core wrapper control inputs, and
v. a core wrapper serial output;
(b) a test access mechanism having a data bus input, wrapper parallel outputs coupled to the core wrapper parallel inputs, wrapper parallel inputs coupled to the core wrapper parallel outputs, a stimulus data clock input, an expected data clock input, a mask data clock input, a compare serial input, compare control inputs, and a compare serial output; and
(c) a test access mechanism controller having:
i. a data bus input;
ii. a stimulus data clock output coupled with the stimulus data clock input,
iii. a wrapper serial output coupled with the core wrapper serial input,
iv. wrapper control outputs coupled with the core wrapper control inputs,
v. a wrapper serial input coupled with the core wrapper serial output,
vi. a compare serial output coupled with the compare serial input,
vii. compare control outputs coupled with the compare control inputs,
viii. a compare serial input coupled with the compare serial output,
ix. an expected data clock output coupled with the expected data clock input, and
x. a mask data clock output coupled with the mask data clock input.
2. The integrated circuit of claim 1 in which the test access mechanism includes a stimulus data memory having inputs coupled to the data bus input, a clock input coupled to the stimulus data clock input, and parallel outputs coupled to the wrapper parallel outputs.
3. The integrated circuit of claim 1 in which the test access mechanism includes a comparator and fail buffer having parallel inputs coupled with the wrapper parallel inputs, a serial input coupled with the compare serial input, control inputs coupled with the compare control inputs, a serial output coupled with the compare serial output, expected data inputs, and mask data inputs.
4. The integrated circuit of claim 1 in which the test access mechanism includes an expected data memory having inputs coupled to the data bus input, a clock input coupled to the expected data clock input, and expected data outputs.
5. The integrated circuit of claim 1 in which the test access mechanism includes a mask data memory having inputs coupled to the data bus input, a clock input coupled to the mask data clock input, and mask data outputs.
6. The integrated circuit of claim 1 in which the test access mechanism includes:
(a) a comparator and fail buffer having parallel inputs coupled with the wrapper parallel inputs, a serial input coupled with the compare serial input, control inputs coupled with the compare control inputs, a serial output coupled with the compare serial output, and expected data inputs; and
(b) an expected data memory having inputs coupled to the data bus input, a clock input coupled to the expected data clock input, and expected data outputs coupled to the expected data inputs.
7. The integrated circuit of claim 1 in which the test access mechanism includes:
(a) a comparator and fail buffer having parallel inputs coupled with the wrapper parallel inputs, a serial input coupled with the compare serial input, control inputs coupled with the compare control inputs, a serial output coupled with the compare serial output, expected data inputs, and mask data inputs;
(b) an expected data memory having inputs coupled to the data bus input, a clock input coupled to the expected data clock input, and expected data outputs coupled to the expected data inputs; and
(c) a mask data memory having inputs coupled to the data bus input, a clock input coupled to the mask data clock input, and mask data outputs coupled to the mask data inputs.
8. The integrated circuit of claim 1 in which the core wrapper includes:
(a) a wrapper control interface coupled to the core wrapper control inputs, the core wrapper control inputs including:
i. a wrapper clock input,
ii. a capture wrapper input,
iii. a shift wrapper input,
iv. an update wrapper input,
v. a transfer wrapper input,
vi. a select wrapper instruction register input, and
vii. a wrapper reset input, and the wrapper control interface including interface control outputs;
(b) a wrapper instruction register coupled to the wrapper serial input, coupled to the wrapper serial output, and coupled to the interface control outputs;
(c) a wrapper bypass register coupled to the wrapper serial input, coupled to the wrapper serial output, and coupled to the interface control outputs;
(d) wrapper boundary registers coupled to the functional inputs and outputs of the functional circuits, coupled to the wrapper serial input, coupled to the wrapper serial output, and coupled to the interface control outputs; and
(e) data register scan paths coupled to the functional circuits, coupled to the wrapper serial input, coupled to the wrapper serial output, and coupled to the interface control outputs.
9. The integrated circuit of claim 1 in which the test access mechanism controller includes:
i. mode inputs,
ii. a clock input,
iii. a select test access mechanism input,
iv. a scan in input,
v. a scan out output, and
vi. a select input.
10. The integrated circuit of claim 9 in which the test access mechanism controller has three mode inputs, Mode 0 , Mode 1 , and Mode 2 .