Memory device communicating with system on chip through at least two channels, electronic device including the same, and operating method of electronic device

1. An electronic device comprising:

a memory device including:

a first memory cell area assigned to a first channel;

a second memory cell area assigned to a second channel;

a first row decoder configured to select a first word line of the first memory cell area;

a first column decoder configured to select a first column select line of the first memory cell area;

a second row decoder configured to select a second word line of the second memory cell area; and

a second column decoder configured to select a second column select line of the second memory cell area; and

a system on chip (SoC) including a first processing unit and a second processing unit, the first processing unit configured to transmit a first command for accessing the first memory cell area to the memory device through the first channel, and the second processing unit configured to transmit a second command for accessing the second memory cell area to the memory device through the second channel,

wherein the memory device is configured such that the first channel has a first bandwidth, the second channel has a second bandwidth, and the first and second bandwidths are different.

2. The electronic device of claim 1 , wherein the memory device further comprises:

first data input/output pins configured to input or output first data through the first channel, the first data being exchanged between the SoC and the first memory cell area; and

second data input/output pins configured to input or output second data through the second channel, the second data being exchanged between the SoC and the second memory cell area.

3. The electronic device of claim 2 , wherein the second bandwidth of the second channel is higher than the first bandwidth of the first channel, and

wherein a number of the second data input/output pins is more than a number of the first data input/output pins.

4. The electronic device of claim 2 , wherein the second bandwidth of the second channel is higher than the first bandwidth of the first channel, and

wherein the memory device is configured such that a transmission speed at which the second data are transmitted through the second data input/output pins is higher than a transmission speed at which the first data are transmitted through the first data input/output pins.

5. The electronic device of claim 1 , wherein the first processing unit is one of a central processing unit (CPU), an image signal processing unit (ISP), and a digital signal processing unit (DSP).

6. The electronic device of claim 1 , wherein the second processing unit is one of a graphics processing unit (GPU), a vision processing unit (VPU), and a neural processing unit (NPU).

7. The electronic device of claim 1 , wherein the SoC is configured to transmit set commands setting a capacity of the first memory cell area and a capacity of the second memory cell area to the memory device.

8. The electronic device of claim 1 , wherein the SoC is further configured to transmit a copy command to the memory device through the first channel or the second channel such that data are copied from the first memory cell area to the second memory cell area or such that data are copied from the second memory cell area to the first memory cell area.

9. A memory device comprising:

a memory cell array including a first memory cell area and a second memory cell area;

a first peripheral circuit configured to access the first memory cell area, in response to a first command transmitted from a system on chip (SoC) through a first channel; and

a second peripheral circuit configured to access the second memory cell area, in response to a second command transmitted from the SoC through a second channel,

wherein the first peripheral circuit includes first data input/output pins, the first peripheral circuit configured to exchange first data with the SoC by inputting or outputting the first data through the first input/output pins,

wherein the second peripheral circuit includes second data input/output pins, the second peripheral circuit configured to exchange second data with the SoC by inputting or outputting the second data through the second input/output pins,

wherein the first peripheral circuit and the second peripheral circuit are configured such that the first channel has a first bandwidth, the second channel has a second bandwidth, and the first and second bandwidths are different,

wherein the first peripheral circuit further includes a first row decoder configured to select a first word line of the first memory cell area and a first column decoder configured to select a first column select line of the first memory cell area, and

wherein the second peripheral circuit further includes a second row decoder configured to select a second word line of the second memory cell area and a second column decoder configured to select a second column select line of the first memory cell area.

10. The memory device of claim 9 , wherein the first peripheral circuit and the second peripheral circuit are configured such that the second bandwidth is higher than the first bandwidth, and

wherein a capacity of the second memory cell area is smaller than a capacity of the first memory cell area.

11. The memory device of claim 10 , wherein the first peripheral circuit and the second peripheral circuit are configured such that an access speed at which the second peripheral circuit accesses the second memory cell area is higher than an access speed at which the first peripheral circuit accesses the first memory cell area.

12. The memory device of claim 9 , wherein the first peripheral circuit further includes a first mode register configured to store a first setting value transmitted from the SoC to set the first memory cell area of the memory cell array, and

wherein the second peripheral circuit further comprises a second mode register configured to store a second setting value transmitted from the SoC to set the second memory cell area of the memory cell array.

13. The memory device of claim 9 , wherein

the first peripheral circuit further includes a third mode register configured to store a third setting value transmitted from the SoC to set a first burst length for the first channel, and

the second peripheral circuit further includes a fourth mode register configured to store a fourth setting value transmitted from the SoC to set a second burst length for the second channel.

14. The memory device of claim 9 , wherein

the first peripheral circuit is further configured to read copy data from the first memory cell area and transmit the copy data to the second peripheral circuit, based on a copy command transmitted through the first channel, and

the second peripheral circuit is further configured to store the copy data in the second memory cell area.

15. The memory device of claim 9 , wherein

the second peripheral circuit is further configured to read copy data from the second memory cell area and transmit the copy data to the first peripheral circuit, based on a copy command transmitted through the second channel, and

the first peripheral circuit is further configured to store the copy data in the first memory cell area.

16. An operating method of an electronic device comprising a memory device and a system on chip (SoC) communicating with the memory device, the method comprising:

assigning a first memory cell area of the memory device to a first channel between the SoC and the memory device and assigning a second memory cell area of the memory device to a second channel between the SoC and the memory device;

performing first data input/output between the SoC and the memory device, based on a first command transmitted to the memory device from the SoC through the first channel; and

performing second data input/output between the SoC and the memory device, based on a second command transmitted to the memory device from the SoC through the second channel,

wherein the first channel has a first bandwidth, the second channel has a second bandwidth, and the first and second bandwidths are different, and

wherein the memory device includes:

a first row decoder configured to select a first word line of the first memory cell area;

a first column decoder configured to select a first column select line of the first memory cell area;

a second row decoder configured to select a second word line of the second memory cell area; and

a second column decoder configured to select a second column select line of the second memory cell area.

17. The method of claim 16 , further comprising:

copying data of the first memory cell area to the second memory cell area, based on a copy command transmitted to the memory device from the SoC through the first channel.

18. The method of claim 16 , further comprising:

copying data of the second memory cell area to the first memory cell area, based on a copy command transmitted to the memory device from the SoC through the second channel.

19. The method of claim 16 , further comprising:

assigning a portion of the first memory cell area assigned to the first channel to the second channel or assigning a portion of the second memory cell area assigned to the second channel to the first channel.

20. The method of claim 16 , further comprising:

setting an operation mode of the first memory cell area through the first channel or setting an operation mode of the second memory cell area through the second channel.