Command address control circuit and semiconductor apparatus and semiconductor system including the command address control circuit and semiconductor apparatus
A semiconductor apparatus includes a command address control circuit. The command address control circuit is configured to receive a row command address signal and a column command address signal, and is configured to selectively invert the row command address signal and the column command address signal based on a logic level of at least one bit of the row command address signal.
1. A semiconductor apparatus comprising a command address control circuit configured to:
receive a row command address signal and a column command address signal, and
invert all bits of the row command address signal and the column command address signal when at least one bit within the row command address signal is at a first logic level, and non-invert all bits of the row command address signal and the column command address signal when the at least one bit within the row command address signal is at a second logic level.
2. The semiconductor apparatus of claim 1 , wherein the command address control circuit is configured to receive the row command address signal and the column command address signal by receiving a command address signal during a plurality of cycles of a clock signal.
3. The semiconductor apparatus of claim 1 , wherein the command address control circuit is configured to correct an error of the row command address signal and the column command address signal based on at least one bit of the column command address signal.
4. A semiconductor apparatus comprising a command generating circuit configured to:
generate a row command address signal and a column command address signal, wherein the row command address signal comprises one bit that includes inversion information for selectively inverting the row command address signal and the column command address signal, and the column command address signal comprises one bit that includes a parity for detecting and correcting an error of the row command address signal and the column command address signal, and
transmit the row command address signal and the column command address signal in synchronization with a clock signal.
5. The semiconductor apparatus of claim 4 , wherein the command generating circuit is configured to transmit the row command address signal and the column command address signal by transmitting a command address signal during a plurality of cycles of the clock signal.
6. A command address control circuit comprising:
an inversion circuit configured to:
receive a row command address signal and a column command address signal, and
invert all bits of the row command address signal and the column command address signal to generate an internal row command address signal and an internal column command address signal when at least one bit within the row command address signal is at a first logic level, and non-invert all bits of the row command address signal and the column command address signal to generate the internal row command address signal and the internal column command address signal when the at least one bit within the row command address signal is at a second logic level;
a row control circuit configured to generate a row command signal and a row address signal based on the internal row command address signal; and
a column control circuit configured to generate a column command signal and a column address signal based on the internal column command address signal.
7. The command address control circuit of claim 6 , wherein the inversion circuit inverts, when the one bit is at the first logic level, all bits of the row command address signal and the column command address signal to generate the internal row command address signal and the internal column command address signal, and
the inversion circuit non-inverts, when the one bit is at the second logic level, all bits of the row command address signal and the column command address signal to generate the internal row command address signal and the internal column command address signal.
8. The command address control circuit of claim 6 , wherein the row control circuit comprises:
a row command decoder configured to be selectively activated based on a first mask signal and configured to decode the internal row command address signal to generate the row command signal;
a row address decoder configured to generate the row address signal from the internal row command address signal based on the row command signal; and
a first command type detecting circuit configured to detect whether the row command signal is of a first type or a second type to generate the first mask signal.
9. The command address control circuit of claim 8 , wherein the column control circuit comprises:
a column command decoder configured to be selectively activated based on a second mask signal and configured to decode the internal column command address signal to generate the column command signal;
a column address decoder configured to generate the column address signal from the internal column command address signal based on the column command signal; and
a second command type detecting circuit configured to detect whether the column command signal is of a first type or a second type to generate the second mask signal.
10. The command address control circuit of claim 6 , further comprising an error correcting circuit configured to correct an error of the row command address signal and the column command address signal based on one bit of the column command address signal.