Semiconductor package with improved flatness of an insulating layer formed on patterns
A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.
1. A semiconductor package comprising:
a support member having first and second surfaces opposing each other, having a cavity penetrating through the first and second surfaces, and including a wiring structure;
a semiconductor chip disposed in the cavity and having an active surface having connection pads disposed thereon;
a connection member including a first insulating layer disposed on the second surface of the support member, a first redistribution layer on the first insulating layer, and a plurality of first vias penetrating through the first insulating layer and connecting the wiring structure and the connection pads to the first redistribution layer; and
an encapsulant encapsulating the semiconductor chip disposed in the cavity and covering the first surface of the support member,
wherein the wiring structure includes wiring patterns disposed on the second surface of the support member, each of the wiring patterns having a thickness greater than that of the first redistribution layer;
the first insulating layer includes a first insulating coating disposed on the second surface of the support member and covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating, and
the first insulating coating is interposed between the second insulating coating and the wiring structure.
2. The semiconductor package of claim 1 , wherein the first and second insulating coatings are formed of the same material.
3. A semiconductor package comprising:
a support member having first and second surfaces opposing each other, having a cavity penetrating through the first and second surfaces, and including a wiring structure;
a semiconductor chip disposed in the cavity and having an active surface having connection pads disposed thereon;
a connection member including a first insulating layer disposed on the second surface of the support member, a first redistribution layer on the first insulating layer, and a plurality of first vias penetrating through the first insulating layer and connecting the wiring structure and the connection pads to the first redistribution layer; and
an encapsulant encapsulating the semiconductor chip disposed in the cavity and covering the first surface of the support member,
wherein the wiring structure includes wiring patterns disposed on the second surface of the support member, each of the wiring patterns having a thickness greater than that of the first redistribution layer,
the first insulating layer includes a first insulating coating disposed on the second surface of the support member and covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating, and
each of the first and second insulating coatings includes a photoimagable dielectric (PID) resin.
4. The semiconductor package of claim 1 , wherein the wiring patterns disposed on the second surface of the support member are protruding wiring patterns, and
a minimum thickness of a portion of the first insulating coating disposed between the wiring patterns is smaller than that of the wiring patterns.
5. The semiconductor package of claim 1 , wherein the wiring structure includes additional wiring patterns disposed on the first surface of the support member and through-vias penetrating through the first and second surfaces of the support member and connecting the wiring patterns and the additional wiring patterns to each other.
6. The semiconductor package of claim 1 , wherein the connection member further includes a second insulating layer disposed on the first redistribution layer, a second redistribution layer disposed on the second insulating layer, and a plurality of second vias penetrating through the second insulating layer and connecting the first redistribution layer and the second redistribution layer to each other.
7. The semiconductor package of claim 6 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.
8. The semiconductor package of claim 6 , wherein the second insulating layer includes a third insulating coating disposed on the first insulating layer and covering the first redistribution layer and a fourth insulating coating disposed on the third insulating coating and having a higher level of flatness than that of the third insulating coating.
9. The semiconductor package of claim 1 , further comprising a passivation layer disposed on the connection member, underbump metal layers penetrating through the passivation layer and connected to the first redistribution layer, and electrical connection structures disposed on the underbump metal layers.
10. The semiconductor package of claim 1 , wherein the wiring patterns protrude from or are concavely disposed on the second surface of the support member.
11. The semiconductor package of claim 1 , wherein the first and second insulating coatings are formed of different materials.