IP Library › Granted Patent US 10,957,543
Granted Patent B2
US 10,957,543 · App. 16/015,743 · Granted Mar 23, 2021

Device and method of dielectric layer

Inventors: Yu-Yun Peng (Hsinchu, TW); Chung-Chi Ko (Nantou County, TW); Keng-Chu Lin (Pingtung County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L21/28158H01L21/022H01L21/0217H01L21/02126H01L21/02164H01L21/02167H01L21/02208H01L21/02211H01L21/02274H01L21/76224
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Quick Facts
Patent No.
US 10,957,543
App. No.
16/015,743
Granted
Mar 23, 2021
Kind
B2
Abstract

A method includes forming an interlayer dielectric (ILD) and a gate structure over a substrate. The gate structure is surrounded by the ILD. The gate structure is etched to form a recess. A first dielectric layer is deposited over sidewalls and a bottom of the recess and over a top surface of the ILD using a first Si-containing precursor. A second dielectric layer is deposited over and in contact with the first dielectric layer using a second Si-containing precursor different from the first Si-containing precursor. A third dielectric layer is deposited over and in contact with the second dielectric layer using the first Si-containing precursor. Portions of the first, second, and third dielectric layer over the top surface of the ILD are removed.

Claims (39)

1. A method comprising:

forming a patterned mask over a substrate;

etching the substrate to form a plurality of fins by using the patterned mask as an etching mask;

depositing a first dielectric layer over sidewalls and a bottom of a trench between the fins and over a top surface of the patterned mask using a first Si-containing precursor, wherein the first precursor comprises Si w R x H y Cl z , w=1 or 2, and (x+y+z)>0;

depositing a second dielectric layer over and in contact with the first dielectric layer using a second Si-containing precursor, wherein the second precursor comprises Si(CH 2 )SiR′ a H b Cl c , where R′ is CH 3 or C 2 H 5 , (a+b+c)=6;

depositing a third dielectric layer over and in contact with the second dielectric layer using the first Si-containing precursor; and

removing excess portions of the first, second, and third dielectric layers over top surfaces of the fins.

2. The method of claim 1 , wherein the first, second, and third dielectric layers are deposited in the same chamber.

3. The method of claim 1 , wherein the first, second, and third dielectric layers are deposited at substantially the same temperature.

4. The method of claim 1 , wherein depositing the first dielectric layer is performed using a nitrogen-containing process gas.

5. The method of claim 1 , wherein depositing the second dielectric layer is performed using an oxygen-containing process gas.

6. The method of claim 1 , wherein depositing the third dielectric layer is performed using a nitrogen-containing process gas.

7. The method of claim 1 , wherein the first dielectric layer is substantially free from Si-C-Si.

8. The method of claim 1 , wherein the second dielectric layer comprises Si-C-Si.

9. The method of claim 1 , further comprising:

forming a fourth dielectric layer over and in contact with the third dielectric layer using the second Si-containing precursor.

10. The method of claim 1 , wherein the first dielectric layer comprises Si-C-O backbones.

11. A method comprising:

etching a semiconductor substrate to form a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate;

depositing a first liner layer over sidewalls and a bottom of the trench using a first Si-containing precursor, wherein the first precursor comprises Si w R x H y Cl z , w>0, and (x+y+z)>0;

depositing a second liner layer conformally over the first liner layer using a second Si-containing precursor, wherein the second precursor comprises Si(CH 2 )SiR′ a H b Cl c , where R′ is CH 3 or C 2 H 5 , (a+b+c)=6;

depositing a third liner layer conformally over the second liner layer using the first Si-containing precursor;

filling a dielectric material into the trench and over the third liner layer; and

removing excess portions of the dielectric material over the top surface of the semiconductor substrate.

12. The method of claim 11 , further comprising:

depositing a fourth liner layer conformally over the third liner layer using the second Si-containing precursor to fill the dielectric material into the trench.

13. The method of claim 11 , wherein the first Si-containing precursor comprises Si-Si.

14. The method of claim 11 , wherein the second Si-containing precursor comprises Si-C-Si.

15. A method comprising:

forming a trench in a substrate;

forming a composite dielectric layer into the trench, wherein forming the composite dielectric layer comprises:

depositing a first dielectric layer in the trench using a first precursor, wherein the first precursor comprises Si w R x H y Cl z , where R is CH 3 or C 2 H 5 , w=1 or 2, (x+y+z)=2w+2, and(x+y+z)>0;

depositing a second dielectric layer over the first dielectric layer using a second precursor, wherein the second precursor comprises Si(CH 2 )SiR′ a H b Cl c , where R′ is CH 3 or C 2 H 5 , (a+b+c)=6, and (a+b+c)>0; and

performing a CMP process to the first dielectric layer and the second dielectric layer until a top surface of the substrate is exposed.

16. The method of claim 15 , further comprising performing depositing the first dielectric layer and depositing the second dielectric layer in an alternate manner.

17. The method of claim 15 , wherein the first precursor further comprises C x H y , where 2≤x≤4.

18. The method of claim 15 , wherein a carbon-containing material is not added during depositing the first dielectric layer, such that a carbon concentration in the second dielectric layer is higher than a carbon concentration in the first dielectric layer.

19. The method of claim 15 , wherein depositing the first dielectric layer is performed using a process gas comprising nitrogen, such that a nitrogen concentration in the first dielectric layer is higher than a nitrogen concentration in the second dielectric layer.

20. The method of claim 15 , wherein depositing the first dielectric layer and depositing the second dielectric layer are performed in a same chamber with a same temperature.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2018
From: PENG, YU-YUN; KO, CHUNG-CHI; LIN, KENG-CHU
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 046195/0870 →
Continuity (2)
Provisional Application 62565696 · Sep 29, 2017
Related Publication 20190103276A1 · Apr 4, 2019