Nanosheet transistor gate structure having reduced parasitic capacitance
Embodiments are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device on a substrate. The fabrication operations include, forming a channel stack over the substrate, wherein the channel stack include stacked and spaced apart channel nanosheets. A metal gate is formed adjacent to end regions of the channel stack and around and between the stacked and spaced apart channel nanosheets. A permanent dummy gate is formed above the channel stack.
1. A method of fabricating a semiconductor device, the method comprising:
performing fabrication operations to form a nanosheet field effect transistor device on a substrate, wherein the fabrication operations include:
forming a channel stack over the substrate, wherein the channel stack comprises stacked and spaced apart channel nanosheets;
forming a metal gate located adjacent to end regions of the channel stack and further located around and between the stacked and spaced apart channel nanosheets; and
forming a permanent dummy gate above the channel stack.
2. The method of claim 1 further comprising forming a source or a drain (S/D) region above the substrate and adjacent to the channel stack.
3. The method of claim 2 further comprising forming a S/D contact communicatively coupled to the S/D region.
4. The method of claim 3 , wherein the S/D contact is adjacent to and spaced apart from the permanent dummy gate.
5. The method of claim 4 , wherein a dielectric gate spacer is adjacent the permanent dummy gate.
6. The method of claim 5 , wherein the dielectric gate spacer is between the permanent dummy gate and the S/D contact.
7. The method of claim 6 , wherein the permanent dummy gate, the dielectric gate spacer and the S/D contact do not generate parasitic capacitance.
8. The method of claim 1 further comprising forming a gate contact communicatively coupled to the metal gate.
9. The method of claim 8 , wherein the gate contact is adjacent to and spaced apart from the permanent dummy gate.
10. The method of claim 9 , wherein a dielectric cap region is adjacent the permanent dummy gate.
11. The method of claim 10 , wherein the dielectric cap region is between the permanent dummy gate and the gate contact.
12. The method of claim 11 , wherein the permanent dummy gate, the dielectric cap region and the gate contact do not generate parasitic capacitance.
13. A nanosheet field effect transistor device comprising:
a channel stack formed over a substrate, wherein the channel stack comprises stacked and spaced apart channel nanosheets;
a metal gate located adjacent to end regions of the channel stack and further located around and between the stacked and spaced apart channel nanosheets; and
a permanent dummy gate formed above the channel stack.
14. The device of claim 13 further comprising forming a source or a drain (S/D) region above the substrate and adjacent to the channel stack.
15. The device of claim 14 further comprising a S/D contact communicatively coupled to the S/D region.
16. The device of claim 15 , wherein the S/D contact is adjacent to and spaced apart from the permanent dummy gate.
17. The device of claim 16 , wherein a dielectric gate spacer is adjacent the permanent dummy gate.
18. The device of claim 17 , wherein the dielectric gate spacer is between the permanent dummy gate and the S/D contact.
19. The device of claim 18 , wherein the permanent dummy gate, the dielectric gate spacer and the S/D contact do not generate parasitic capacitance.
20. The device of claim 19 further comprising:
forming a gate contact communicatively coupled to the metal gate;
wherein the gate contact is adjacent to and spaced apart from the permanent dummy gate;
wherein a dielectric cap region is between the permanent dummy gate and the gate contact;
wherein the permanent dummy gate, the dielectric cap region and the gate contact do not generate parasitic capacitance.