Integrating and isolating NFET and PFET nanosheet transistors on a substrate

1. A method of forming an insulation region during fabrication of a nanosheet channel field effect transistor (FET), the method comprising:

forming a first sacrificial nanosheet across from a major surface of a substrate, wherein the first sacrificial nanosheet comprises a first semiconductor material at a concentration percentage less than or equal to about fifty percent;

forming a first nanosheet stack on an opposite side of the first sacrificial nanosheet from the major surface of the substrate;

wherein the first nanosheet stack comprises alternating channel nanosheets and sacrificial stack nanosheets;

wherein a thickness dimension of the first sacrificial nanosheet is greater than a thickness dimension of at least one of the alternating channel nanosheets; and

performing an oxidation operation that converts the first sacrificial nanosheet to a dielectric oxide, wherein the insulation region comprises the dielectric oxide.

2. The method of claim 1 further comprising depositing a protective liner over the first nanosheet stack, wherein the protective liner protects the first nanosheet stack from being oxidized the by the oxidation operation.

3. The method of claim 1 , wherein:

the first nanosheet stack comprises an elongated fin shape; and

the first sacrificial nanosheet comprises an elongated fin shape.

4. The method of claim 3 further comprising forming oxide regions adjacent elongated sidewalls of the fin shaped first sacrificial nanosheet.

5. The method of claim 4 , wherein top surfaces of the oxide regions are below a top surface of the fin shaped first sacrificial nanosheet.

6. The method of claim 5 , wherein the oxide region is formed prior to the oxidation operation.

7. The method of claim 5 , wherein the insulation region comprises the dielectric oxide and the oxide regions.

8. The method of claim 1 , wherein the sacrificial nanosheet comprises silicon germanium.

9. The method of claim 8 , wherein the first semiconductor material comprises germanium.

10. The method of claim 9 , wherein the channel nanosheets comprise silicon.

11. A method of forming insulation regions during the fabrication of nanosheet channel field effect transistor (FET) devices, the method comprising:

forming a substrate comprising a major surface having a first region and a second region;

forming a sacrificial nanosheet across from the major surface of the substrate, wherein the sacrificial nanosheet comprises a first sacrificial nanosheet across from the first region and a second sacrificial nanosheet across from the second region;

forming a nanosheet stack on an opposite side of the sacrificial nanosheet from the major surface of the substrate, wherein the nanosheet stack comprises a first nanosheet stack on an opposite side of the first sacrificial nanosheet from the first region, wherein the nanosheet stack further comprises a second nanosheet stack on an opposite side of the second sacrificial nanosheet from the second region, wherein the first nanosheet stack comprises alternating first channel nanosheets and first sacrificial stack nanosheets, wherein the second nanosheet stack comprises alternating second channel nanosheets and second sacrificial stack nanosheets;

wherein the first sacrificial nanosheet comprises a first semiconductor material at a first concentration percentage less than or equal to about fifty percent;

wherein the second sacrificial nanosheet comprises the first semiconductor material at a second concentration percentage less than or equal to about fifty percent;

wherein a thickness dimension of the first sacrificial nanosheet is greater than a thickness dimension of at least one of the first alternating channel nanosheets;

wherein a thickness dimension of the second sacrificial nanosheet is greater than a thickness dimension of at least one of the second alternating channel nanosheets; and

performing an oxidation operation that converts the first sacrificial nanosheet and the second sacrificial nanosheet to a dielectric oxide, wherein the insulation regions comprises the dielectric oxide.

12. The method of claim 11 further comprising:

depositing a first protective liner over the first nanosheet stack, wherein the first protective liner protects the first nanosheet stack from being oxidized the by the oxidation operation; and

depositing a second protective liner over the second nanosheet stack, wherein the second protective liner protects the second nanosheet stack from being oxidized the by the oxidation operation.

13. The method of claim 11 , wherein the first nanosheet stack, the second nanosheet stack, the first sacrificial nanosheet and the second sacrificial nanosheet each comprise an elongated fin shape.

14. The method of claim 13 further comprising forming oxide regions adjacent elongated sidewalls of the fin shaped first sacrificial nanosheet and elongated sidewalls of the fin shaped second sacrificial nanosheet.

15. The method of claim 14 , wherein top surfaces of the oxide regions are below a top surface of the fin shaped first sacrificial nanosheet and below a top surface of the fin shaped second sacrificial nanosheet.

16. The method of claim 15 , wherein the oxide region is formed prior to the oxidation operation.

17. The method of claim 15 , wherein the insulation region comprises the dielectric oxide and the oxide regions.

18. The method of claim 11 , wherein the first sacrificial nanosheet and the second sacrificial each comprise silicon germanium.

19. The method of claim 18 , wherein the first semiconductor material comprises germanium.

20. The method of claim 19 , wherein the first channel nanosheet and the second channel nanosheet each comprise silicon.