Method of manufacturing semiconductor device that uses bonding layer to join semiconductor substrates together
Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first interconnection structure over a first semiconductor substrate;
applying a first bonding layer in physical contact with the first interconnection structure;
forming a second interconnection structure over a second semiconductor substrate; and
bonding the second interconnection structure to the first bonding layer, wherein the first interconnection structure is in physical contact with a first gate contact.
2. The method of claim 1 , wherein the second interconnection structure is in physical contact with a second gate contact.
3. The method of claim 1 , wherein the second interconnection structure is adjacent to a third interconnection structure that is in physical contact with a second gate contact.
4. The method of claim 1 , wherein the forming the first interconnection structure over the first semiconductor substrate utilizes either a first damascene process or a first dual damascene process.
5. The method of claim 1 , wherein the first interconnection structure has a height of between about 1 nm and about 5 nm.
6. A method of manufacturing a semiconductor device, the method comprising:
depositing a first bonding dielectric layer in physical contact with one of either a gate electrode or a gate electrode contact;
embedding a first conductive bonding material through the first bonding dielectric layer and in physical contact with the one of either the gate electrode or the gate electrode contact; and
bonding a conductive material of a first semiconductor die directly to the first conductive bonding material.
7. The method of claim 6 , wherein the depositing the first bonding dielectric layer deposits the first bonding dielectric layer in physical contact with the gate electrode.
8. The method of claim 6 , wherein the depositing the first bonding dielectric layer deposits the first bonding dielectric layer in physical contact with the gate electrode contact.
9. The method of claim 6 , further comprising depositing a fill material adjacent to the first semiconductor die after the bonding the conductive material.
10. The method of claim 9 , further comprising forming through fill vias to extend from a first side of the fill material to a second side of the fill material.
11. The method of claim 10 , further comprising:
depositing a first interconnect dielectric layer over the first semiconductor die and the fill material; and
embedding a first interconnect conductive material into the first interconnect dielectric layer using one of either a damascene process or a dual damascene process.
12. The method of claim 10 , further comprising:
bonding a second semiconductor die to the first semiconductor die on an opposite side of the first semiconductor die from the first bonding dielectric layer;
depositing a second fill material adjacent to the second semiconductor die; and
forming second through fill vias to extend from a first side of the second fill material to a second side of the second fill material.
13. A method of manufacturing a semiconductor device, the method comprising:
depositing a first bonding dielectric layer over a first semiconductor wafer and in physical contact with one of a first gate stack, a first gate electrode contact, a first interconnection structure in physical contact with the first gate electrode contact, or a second interconnection structure adjacent to the first interconnection structure;
embedding a first bonding conductor into the first bonding dielectric layer;
depositing a second bonding dielectric layer over a second semiconductor wafer different from the first semiconductor wafer and in physical contact with one of a second gate stack, a second gate electrode contact, a third interconnection structure in physical contact with the second gate electrode contact, or a fourth interconnection structure adjacent to the third interconnection structure;
embedding a second bonding conductor into the second bonding dielectric layer;
activating the first bonding dielectric layer and the second bonding dielectric layer; and
contacting the first bonding dielectric layer and the second bonding dielectric layer.
14. The method of claim 13 , wherein the depositing the first bonding dielectric layer is deposited in physical contact with the first gate stack.
15. The method of claim 13 , wherein the depositing the first bonding dielectric layer is deposited in physical contact with the first gate electrode contact.
16. The method of claim 13 , wherein the depositing the first bonding dielectric layer is deposited in physical contact with the first interconnection structure.
17. The method of claim 13 , wherein the depositing the first bonding dielectric layer is deposited in physical contact with the second interconnection structure.
18. The method of claim 13 , further comprising thinning the second semiconductor wafer to expose through substrate vias.
19. The method of claim 13 , wherein the embedding the second bonding conductor utilizes a damascene process.
20. The method of claim 13 , wherein the embedding the second bonding conductor utilizes a dual damascene process.