Integrated circuit structure to reduce soft-fail incidence and method of forming same
This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.
1. An integrated circuit (IC) structure comprising:
a semiconductor structure;
a first source/drain region formed in the semiconductor structure;
a second source/drain region formed in the semiconductor structure;
a metal gate positioned on the semiconductor structure adjacent to and between the first source/drain region and the second source/drain region, the metal gate including a first metal;
a metal cap positioned on the metal gate, wherein the metal cap has a different metal composition than the first metal;
a first dielectric cap layer having a bottom surface positioned on and in direct contact with at least a portion of an upper surface of the semiconductor structure;
a first inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein a height of an upper surface of the first ILD above the semiconductor structure is greater than a height of an upper surface of the metal gate above the semiconductor structure;
a second dielectric cap layer positioned on the first ILD and above the metal cap;
a first contact on and in electrical contact with an upper surface of the metal cap, wherein the second dielectric cap layer laterally abuts a portion of the first contact; and
a second contact extending through the first dielectric cap layer to the first source/drain region, wherein the second dielectric cap layer laterally abuts a portion of the second contact, and wherein the second contact is electrically isolated from the first contact.
2. The integrated circuit structure of claim 1 , wherein the metal cap includes ruthenium (Ru).
3. The integrated circuit structure of claim 1 , further comprising:
a through silicon via (TSV) positioned within the semiconductor structure; and
a second contact extending through the first dielectric cap layer to the TSV,
wherein the second dielectric cap layer laterally abuts a portion of the second contact, and wherein the second contact is electrically isolated from the first contact.
4. The integrated circuit structure of claim 1 , wherein the semiconductor structure includes a fin, wherein the first source/drain region and second source/drain region are both formed in the fin, and wherein the metal gate is positioned on the fin.
5. The integrated circuit structure of claim 4 , wherein the metal gate additionally contacts at least a portion of a lateral side surface of the fin.
6. The integrated circuit structure of claim 4 , wherein the semiconductor structure includes:
a second fin;
a third source/drain region formed in the second fin;
a fourth source/drain region formed in the second fin;
wherein the metal gate is additionally positioned on the second fin between the third source/drain region and the fourth source/drain region.
7. The integrated circuit structure of claim 1 , further comprising:
a nanowire positioned above the semiconductor structure and between the first source/drain region and the second source/drain region, wherein the metal gate surrounds and contacts at least a portion of the nanowire.
8. The integrated circuit structure of claim 1 , wherein the metal gate comprises:
a high-K dielectric liner on the semiconductor structure;
a work function metal in contact with the liner; and
a conductive plug in contact with the work function metal and including the first metal,
wherein the work function metal has a different metal composition than the metal cap.
9. The integrated circuit structure of claim 8 , wherein the work function metal includes titanium nitride (TiN).
10. The integrated circuit structure of claim 8 , wherein the work function metal includes titanium aluminum carbide (Ti 3 AlC 2 ).
11. The integrated circuit structure of claim 1 , wherein the metal cap includes cobalt (Co).
12. The integrated circuit structure of claim 1 , wherein the metal cap includes tungsten (W).
13. An integrated circuit (IC) structure comprising:
a semiconductor structure;
a first source/drain region formed in the semiconductor structure;
a second source/drain region formed in the semiconductor structure;
a gate stack positioned on the semiconductor structure adjacent to and between the first source/drain region and the second source/drain region, the gate stack including:
a high-K dielectric liner on the semiconductor structure;
a work function metal in contact with the liner; and
a conductive plug in contact with the work function metal;
a metal cap positioned on the gate stack, wherein the metal cap has a different metal composition than the work function metal and the conductive plug, and wherein the metal cap has a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm;
a first dielectric cap layer positioned on at least a portion of the semiconductor structure;
a first inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the gate stack, wherein a height of an upper surface of the first ILD above the semiconductor structure is greater than a height of an upper surface of the gate stack above the semiconductor structure;
a second dielectric cap layer positioned on the first ILD and above the metal cap;
a gate contact on and in electrical contact with an upper surface of the metal cap, wherein the second dielectric cap layer laterally abuts a portion of the gate contact; and
a second contact extending through the first dielectric cap layer above and in electrical contact with the first source/drain region, wherein the second dielectric cap layer laterally abuts a portion of the second contact, and wherein the second contact is electrically isolated from the gate contact.
14. The integrated circuit structure of claim 13 , wherein the metal cap includes ruthenium (Ru).
15. The integrated circuit structure of claim 13 , wherein the semiconductor structure includes a fin, the integrated circuit further comprising:
a first spacer positioned on the fin adjacent to the gate stack, wherein a height of an upper surface of the first spacer above the fin is greater than a height of an upper surface of the gate stack above the fin; and
a second spacer positioned on the fin adjacent to the gate stack, wherein a height of an upper surface of the second spacer above the fin is greater than the height of the upper surface of the gate stack above the fin,
wherein the first source/drain region and the second source/drain region are both formed in the fin, and wherein the gate stack is positioned on the fin between the first spacer and the second spacer and contacts at least a portion of a lateral side surface of the fin.
16. The integrated circuit structure of claim 13 , wherein the work function metal includes titanium nitride (TiN).
17. The integrated circuit structure of claim 13 , wherein the metal cap includes cobalt (Co).
18. The integrated circuit structure of claim 13 , wherein the metal cap includes tungsten (W).
19. The integrated circuit structure of claim 13 , wherein the work function metal includes titanium aluminum carbide (Ti 3 AlC 2 ).