Asymmetric pass field-effect transistor for nonvolatile memory
A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.
1. A method of manufacturing a memory device, comprising:
patterning a gate layer deposited over a surface of a substrate to form a gate of a first memory transistor and a gate of a first pass transistor of a first non-volatile memory (NVM) cell;
implanting dopants into the surface of the substrate to form a source and a drain adjacent to the gate of the first memory transistor and a source and a drain adjacent to the gate of the first pass transistor;
masking at least the drain adjacent to the gate of the first pass transistor; and
performing a halo implant implanting dopants around the source adjacent to the gate of the first pass transistor to form an asymmetric first pass transistor,
wherein implanting dopants into the surface of the substrate to form a source and a drain adjacent to the gate of the first memory transistor comprises a first lightly doped drain (LDD) process, and implanting dopants into the surface of the substrate to form a source and a drain adjacent to the gate of the first pass transistor comprises a second LDD process.
2. The method of claim 1 wherein the halo implant is performed at an angle so that the dopants are implanted at least partially under the gate of the first pass transistor.
3. The method of claim 1 wherein the halo implant is lightly doped halo implant.
4. The method of claim 1 wherein implanting dopants into the surface of the substrate to form source and drains of the first memory transistor and first pass transistor comprises implanting dopants of a first type, and wherein performing the halo implant comprises implanting dopants of a second type, different from the first type.
5. The method of claim 1 wherein an implant dose or energy for the first LDD process is different from an implant dose or energy for the second LDD process.
6. A method of manufacturing a memory device, comprising:
patterning a gate layer deposited over a surface of a substrate to form a gate of a first memory transistor and a gate of a first pass transistor of a first non-volatile memory (NVM) cell;
implanting dopants into the surface of the substrate to form a source and a drain adjacent to the gate of the first memory transistor and a source and a drain adjacent to the gate of the first pass transistor;
masking at least the drain adjacent to the gate of the first pass transistor; and
performing a halo implant implanting dopants around the source adjacent to the gate of the first pass transistor to form an asymmetric first pass transistor,
wherein implanting dopants into the surface of the substrate to form sources adjacent to the gate of the first memory transistor and to the gate of the first pass transistor comprises implanting dopants into the surface of the substrate at an implant dose or energy different from an implant dose or energy for forming drains adjacent to the gate of the first memory transistor and to the gate of the first pass transistor.
7. The method of claim 6 wherein the halo implant is performed at an angle so that the dopants are implanted at least partially under the gate of the first pass transistor.
8. The method of claim 6 wherein the halo implant is lightly doped halo implant.
9. The method of claim 6 wherein implanting dopants into the surface of the substrate to form source and drains of the first memory transistor and first pass transistor comprises implanting dopants of a first type, and wherein performing the halo implant comprises implanting dopants of a second type, different from the first type.
10. The method of claim 6 wherein:
patterning the gate layer further comprises patterning the gate layer to form a gate of a second memory transistor and a gate of a second pass transistor of a second non-volatile memory (NVM) cell; and
implanting dopants into the surface of the substrate further comprises implanting dopants to form a source and a drain adjacent to the gate of the second memory transistor and a source and a drain adjacent to the gate of the second pass transistor.
11. The method of claim 10 wherein:
masking at least the drain adjacent to the gate of the first pass transistor further comprises masking the drain adjacent to the gate of the second pass transistor; and
performing a halo implant further comprises implanting dopants around the source adjacent to the gate of the second pass transistor to form an asymmetric second pass transistor.
12. The method of claim 11 wherein:
further comprising forming a common source line (CSL) coupled with at least a source of one of the first pass transistor or the second pass transistor.
13. A method of manufacturing a memory device, comprising:
patterning a gate layer deposited over a surface of a substrate to form a gate of a first memory transistor and a gate of a first pass transistor of a first non-volatile memory (NVM) cell, and patterning the gate layer to form a gate of a second memory transistor and a gate of a second pass transistor of a second non-volatile memory (NVM) cell;
implanting dopants into the surface of the substrate to form a source and a drain adjacent to the gate of the first memory transistor and a source and a drain adjacent to the gate of the first pass transistor, and to form a source and a drain adjacent to the gate of the second memory transistor and a source and a drain adjacent to the gate of the second pass transistor;
masking at least the drain adjacent to the gate of the first pass transistor; and
performing a halo implant implanting dopants around the source adjacent to the gate of the first pass transistor to form an asymmetric first pass transistor.
14. The method of claim 13 wherein:
masking at least the drain adjacent to the gate of the first pass transistor further comprises masking the drain adjacent to the gate of the second pass transistor; and
performing a halo implant further comprises implanting dopants around the source adjacent to the gate of the second pass transistor to form an asymmetric second pass transistor.
15. The method of claim 14 further comprising forming a common source line (CSL) coupled with at least a source of one of the first pass transistor or the second pass transistor.
16. A method of manufacturing a memory device, comprising:
forming a gate of a first pass transistor of a first non-volatile memory (NVM) cell and a gate of a second pass transistor of a second NVM cell;
forming a single, contiguous shared source adjacent to and between the gate of the first pass transistor and the gate of the second pass transistor, and forming drains adjacent to the gates of the first and second pass transistors on opposite sides from the shared source;
masking the drains adjacent to the gates of the first and the second pass transistors; and
performing a halo implant implanting dopants around the shared source to form asymmetric first and second pass transistors,
wherein forming the shared source and the drains comprises a lightly doped drain (LDD) process.
17. The method of claim 16 wherein the halo implant is performed at an angle so that the dopants are implanted at least partially under the gates of the first and second pass transistors.
18. The method of claim 16 wherein the halo implant is lightly doped halo implant.
19. The method of claim 16 wherein forming the shared source and the drains comprises implanting dopants of a first type, and wherein performing the halo implant comprises implanting dopants of a second type, different from the first type.
20. The method of claim 16 wherein forming the shared source comprises implanting dopants at an implant dose or energy different from an implant dose or energy for forming drains adjacent to the gates of the first and second pass transistors.