IP Library Granted Patent US 10,636,756
Granted Patent B2
US 10,636,756 · App. 16/027,731 · Granted Apr 28, 2020

Semiconductor device and method of forming protrusion E-bar for 3D SIP

Inventors: DeokKyung Yang (Incheon-Si, KR); HunTeak Lee (Gyeongi-do, KR); OhHan Kim (In-Cheon, KR); HeeSoo Lee (Kyunggi-do, KR); DaeHyeok Ha (Kyunggi-do, KR); Wanil Lee (Incheon-Si, KR)
Assignee: STATS ChipPAC Pte. Ltd.
H01L24/08H01L23/538H01L24/45H01L2224/32145H01L2224/32225H01L2224/48227H01L2224/73204H01L2224/73253H01L2924/15331
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Quick Facts
Patent No.
US 10,636,756
App. No.
16/027,731
Granted
Apr 28, 2020
Kind
B2
Abstract

A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component.

Claims (50)

1. A method of making a semiconductor device, comprising:

providing a first substrate;

disposing a semiconductor die over the first substrate;

providing a second substrate including a conductive post protruding from the second substrate;

disposing the second substrate over the first substrate;

forming an opening in the second substrate aligned with the conductive post; and

forming an interconnect structure in the opening to contact the conductive post.

2. The method of claim 1 , further including depositing an encapsulant around the second substrate and semiconductor die.

3. The method of claim 1 , wherein a portion of the conductive post is embedded within the second substrate.

4. The method of claim 1 , wherein the conductive post includes:

forming a first conductive layer; and

forming a second conductive layer over the first conductive layer, wherein the first conductive layer is wider than the second conductive layer.

5. The method of claim 1 , further including disposing a discrete electrical component over a surface of the first substrate opposite the semiconductor die.

6. The method of claim 5 , further including forming a shielding layer over the discrete electrical component.

7. A method of making a semiconductor device, comprising:

providing a substrate including a conductive post extending from the substrate;

disposing a semiconductor die adjacent to the substrate;

forming an opening extending completely through the substrate to the conductive post; and

forming an interconnect structure in the opening to contact the conductive post.

8. The method of claim 7 , further including depositing an encapsulant around the substrate and semiconductor die.

9. The method of claim 7 , wherein a portion of the conductive post is embedded within the substrate.

10. The method of claim 7 , further including disposing a semiconductor package over the semiconductor device.

11. The method of claim 7 , further including disposing a discrete electrical component over a surface of the substrate opposite the semiconductor die.

12. The method of claim 11 , further including forming a shielding layer over the discrete electrical component.

13. The method of claim 7 , wherein the conductive post includes:

forming a first conductive layer; and

forming a second conductive layer over the first conductive layer.

14. A method of making a semiconductor device, comprising:

providing a first substrate;

disposing a semiconductor die over the first substrate;

disposing a second substrate including a conductive post protruding from the second substrate over the first substrate; and

forming an interconnect structure in an opening in the second substrate and aligned with the conductive post to contact the conductive post.

15. The method of claim 14 , further including depositing an encapsulant around the second substrate and semiconductor die.

16. The method of claim 14 , wherein a portion of the conductive post is embedded within the second substrate.

17. The method of claim 14 , wherein the conductive post includes:

a first conductive layer; and

a second conductive layer formed over the first conductive layer.

18. The method of claim 14 , further including disposing a discrete electrical component over a surface of the first substrate opposite the semiconductor die.

19. The method of claim 18 , further including forming a shielding layer over the discrete electrical component.

20. A method of making a semiconductor device, comprising:

providing a substrate including a conductive post extending from the substrate;

disposing a semiconductor die adjacent to the substrate; and

forming an interconnect structure in an opening which extends substantially through the substrate to contact the conductive post.

21. The method of claim 20 , further including depositing an encapsulant around the substrate and semiconductor die.

22. The semiconductor device of claim 20 , wherein a portion of the conductive post is embedded within the substrate.

23. The semiconductor device of claim 20 , further including disposing a discrete electrical component over a surface of the substrate opposite the semiconductor die.

24. The semiconductor device of claim 23 , further including forming a shielding layer over the discrete electrical component.

25. The semiconductor device of claim 20 , wherein the conductive post includes:

a first conductive layer; and

a second conductive layer formed over the first conductive layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2018
From: YANG, DEOKKYUNG; LEE, HUNTEAK; KIM, OHHAN; LEE, HEESOO; HA, DAEHYEOK; LEE, WANIL
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 046271/0197 →
Continuity (1)
Related Publication 20200013738A1 · Jan 9, 2020