Method and apparatus for virtualizing the micro-op cache
Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from having to be decoded again on subsequent executions. When the control logic determines that micro-operations for one or more fetched instructions are stored in either the micro-operation cache or the conventional cache subsystem, the control logic causes the decode unit to transition to a reduced-power state.
1. A processor comprising:
an instruction cache configured to store a first instruction in a first entry addressable by a first address;
a fetch unit configured to fetch the first instruction from the instruction cache;
a decode unit configured to decode the first instruction into one or more first micro-operations; and
a micro-operation cache configured to store the one or more first micro-operations;
control logic configured to:
write the one or more first micro-operations to the instruction cache, responsive to the one or more first micro-operations being evicted from the micro-operation cache; and
retrieve, via the fetch unit, the one or more first micro-operations instead of the first instruction from the instruction cache, responsive to initiating a fetch, via the fetch unit, of the first instruction.
2. The processor as recited in claim 1 , wherein the control logic is further configured to overwrite the first instruction in the first entry of the instruction cache with the one or more first micro-operations responsive to the one or more first micro-operations being evicted from the micro-operation cache.
3. The processor as recited in claim 1 , wherein the control logic is further configured to write the one or more first micro-operations evicted from the micro-operation cache to the instruction cache responsive to the one or more first micro-operations meeting a first condition.
4. The processor as recited in claim 3 , wherein the first condition is the one or more first micro-operations taking up N or fewer entries in the instruction cache, wherein N is a positive integer.
5. The processor as recited in claim 1 , wherein the processor is configured to send the one or more first micro-operations on a path which bypasses the decode unit responsive to determining the one or more first micro-operations are stored in the instruction cache.
6. The processor as recited in claim 1 , wherein:
the processor further comprises a pre-decode cache;
the control logic is configured to write metadata associated with the one or more first micro-operations to an entry of the pre-decode cache responsive to writing the one or more first micro-operations to the instruction cache; and
the processor is configured to perform parallel lookups of the instruction cache and the pre-decode cache for a fetched instruction.
7. The processor as recited in claim 1 , wherein in response to a determination that the one or more first micro-operations are in the instruction cache, the processor is configured to cause the decode unit to enter a reduced power state.
8. A method comprising:
storing a first instruction in a first entry of an instruction cache, wherein the first instruction is addressable by a first address;
fetching, by a fetch unit, the first instruction from the instruction cache;
decoding, by a decode unit, the first instruction into one or more first micro-operations;
storing the one or more first micro-operations in a micro-operation cache;
writing the one or more first micro-operations to the instruction cache responsive to the one or more first micro-operations being evicted from the micro-operation cache;
retrieving, via the fetch unit, the one or more first micro-operations instead of the first instruction from the instruction cache, responsive to initiating a fetch, via the fetch unit, of the first instruction.
9. The method as recited in claim 8 , further comprising overwriting the first instruction in the first entry of the instruction cache with the one or more first micro-operations responsive to the one or more first micro-operations being evicted from the micro-operation cache.
10. The method as recited in claim 8 , further comprising writing the one or more first micro-operations evicted from the micro-operation cache to the instruction cache responsive to the one or more first micro-operations meeting a first condition.
11. The method as recited in claim 10 , wherein the first condition is the one or more first micro-operations taking up N or fewer entries in the instruction cache, wherein N is a positive integer.
12. The method as recited in claim 8 , further comprising sending the one or more first micro-operations on a path which bypasses the decode unit responsive to determining the one or more first micro-operations are stored in the instruction cache.
13. The method as recited in claim 8 , further comprising
writing metadata associated with the one or more first micro-operations to an entry of a pre-decode cache responsive to writing the one or more first micro-operations to the instruction cache; and
performing parallel lookups of the instruction cache and the pre-decode cache for a fetched instruction.
14. The method as recited in claim 13 , further comprising causing the decode unit to enter a lower power state than a current power state of the decode unit, responsive to determining the one or more first micro-operations are in the instruction cache.
15. A system comprising:
a memory;
a processor coupled to the memory;
wherein the processor is configured to:
store a first instruction in a first entry of an instruction cache, wherein the first entry is addressable by a first address;
fetch, by a fetch unit, the first instruction from the instruction cache;
decode the first instruction into one or more first micro-operations;
write the one or more first micro-operations to the instruction cache responsive to the one or more first micro-operations being evicted from a micro-operation cache;
retrieve, via the fetch unit, the one or more first micro-operations instead of the first instruction from the instruction cache, responsive to initiating a fetch, via the fetch unit, of the first instruction.
16. The system as recited in claim 15 , wherein the processor is further configured to overwrite the first instruction in the first entry of the instruction cache with the one or more first micro-operations responsive to the one or more first micro-operations being evicted from the micro-operation cache.
17. The system as recited in claim 15 , wherein the processor is further configured to write the one or more first micro-operations evicted from the micro-operation cache to the instruction cache responsive to the one or more first micro-operations meeting a first condition.
18. The system as recited in claim 17 , wherein the first condition is the one or more first micro-operations taking up N or fewer entries in the instruction cache, wherein N is a positive integer.
19. The system as recited in claim 15 , wherein the processor is further configured to send the one or more first micro-operations on a path which bypasses the decode unit responsive to determining the one or more first micro-operations are stored in the instruction cache.
20. The system as recited in claim 15 , wherein the processor is further configured to write metadata associated with the one or more first micro-operations to an entry of a pre-decode cache responsive to writing the one or more first micro-operations to the instruction cache.