Processing unit employing micro-operations (micro-ops) random access memory (RAM) as main program memory
Aspects disclosed in the detailed description include a processing unit (PU) employing micro-operations (micro-ops) random access memory (RAM) as main program memory. The micro-ops RAM comprises row circuits each associated with a micro-op and configured to store control signal parameters and output ports configured to be coupled to a register file and one or more execution units. In contrast to fetching and decoding instructions of an ISA in a conventional PU, the processing unit loads a main program comprising micro-ops into the row circuits of the micro-ops RAM. When executing an individual micro-op of the main program, the processing unit activates a row circuit in the micro-ops RAM to cause its stored control signal parameters to be communicated through the output ports of the micro-ops RAM to the register file and/or the one or more execution units and avoids the need for a decoding stage circuit, advantageously decreasing processing latency.
1. An apparatus, comprising:
a processing unit, comprising:
a micro-operations (micro-ops) random access memory (RAM), comprising:
a plurality of row circuits configured to store a plurality of register control signal parameters corresponding to a register micro-op to be processed and a plurality of execution control signal parameters corresponding to an execution micro-op to be executed;
a register file; and
an execution circuit;
the processing unit configured to:
activate a first row circuit of the plurality of row circuits to couple the plurality of register control signal parameters in the first row circuit to the register file to cause one or more operands to be provided to the execution circuit; and
activate a second row circuit of the plurality of row circuits to couple the plurality of execution control signal parameters in the second row circuit to the execution circuit to select an operation of the execution circuit; and
the execution circuit configured to execute the operation based on the one or more operands and the plurality of execution control signal parameters.
2. The apparatus of claim 1 , wherein the first row circuit and the second row circuit are disposed in a common row circuit of the plurality of row circuits.
3. The apparatus of claim 1 , wherein:
the register file further comprises register input ports;
the execution circuit further comprises execution circuit input ports;
the micro-ops RAM further comprises:
a plurality of first output ports coupled to the register input ports; and
a plurality of second output ports coupled to the execution circuit input ports;
the first row circuit is coupled to the plurality of first output ports; and
the second row circuit is coupled to the plurality of second output ports.
4. The apparatus of claim 3 , wherein the register file further comprises register output ports,
wherein the one or more operands are communicated from the register file to the execution circuit through the register output ports.
5. The apparatus of claim 1 , further comprising:
a memory storing a program comprising a plurality of micro-ops; and
the processing unit further configured to:
load the plurality of micro-ops into the plurality of row circuits in the micro-ops RAM.
6. The apparatus of claim 1 , wherein the micro-ops RAM is directly coupled to the register file.
7. The apparatus of claim 1 , wherein the micro-ops RAM is directly coupled to the execution circuit.
8. The apparatus of claim 1 , wherein the processing unit is further configured to activate the first row circuit in a clock cycle.
9. The apparatus of claim 1 integrated into an integrated circuit (IC).
10. The apparatus of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics systems; and a multicopter.
11. A method of operating a processing unit employing a micro-operations (micro-ops) random access memory (RAM), comprising:
providing the micro-ops RAM, the micro-ops RAM comprising:
a plurality of row circuits configured to store a plurality of register control signal parameters corresponding to a register micro-op to be processed and a plurality of execution control signal parameters corresponding to an execution micro-op to be executed;
activating a first row circuit of the plurality of row circuits to couple the plurality of register control signal parameters in the first row circuit to a register file to cause one or more operands to be provided to an execution circuit;
activating a second row circuit of the plurality of row circuits to couple the plurality of execution control signal parameters in the second row circuit to the execution circuit to select an operation of the execution circuit; and
executing the operation based on the one or more operands and the plurality of execution control signal parameters.
12. The method of claim 11 , wherein the first row circuit and the second row circuit are disposed in a common row circuit of the plurality of row circuits.
13. The method of claim 11 , wherein:
the register file further comprises register input ports;
the execution circuit further comprises execution circuit input ports;
the micro-ops RAM further comprises:
a plurality of first output ports coupled to the register input ports; and
a plurality of second output ports coupled to the execution circuit input ports;
the first row circuit is coupled to the plurality of first output ports; and
the second row circuit is coupled to the plurality of second output ports.
14. The method of claim 13 , wherein the register file further comprises register output ports,
wherein activating the first row circuit further comprises:
communicating the one or more operands from the register file to the execution circuit through the register output ports.
15. The method of claim 11 , further comprising:
storing a plurality of micro-ops in a memory; and
loading the plurality of micro-ops into the plurality of row circuits in the micro-ops RAM.
16. The method of claim 11 , further comprising directly coupling the micro-ops RAM to the register file.
17. The method of claim 11 , further comprising directly coupling the micro-ops RAM to the execution circuit.
18. The method of claim 11 , wherein activating the first row circuit further comprises activating the first row circuit in a clock cycle.
19. The method of claim 12 , wherein:
activating the first row circuit further comprises:
activating the first row circuit in a clock cycle; and
activating the second row circuit further comprises:
activating the second row circuit in the clock cycle.
20. An apparatus, comprising:
a processing unit, comprising:
a micro-operations (micro-ops) random access memory (RAM), comprising:
a plurality of row circuits configured to store a plurality of register control signal parameters corresponding to a register micro-op to be processed and a plurality of execution control signal parameters corresponding to an execution micro-op to be executed;
a register file; and
an execution circuit;
means for activating a first row circuit of the plurality of row circuits to couple the plurality of register control signal parameters in the first row circuit to the register file to cause one or more operands to be provided to the execution circuit;
means for activating a second row circuit of the plurality of row circuits to couple the plurality of execution control signal parameters in the second row circuit to the execution circuit to select an operation of the execution circuit; and
means for executing the operation based on the one or more operands and the plurality of execution control signal parameters.
21. The apparatus of claim 20 , wherein the first row circuit and the second row circuit are disposed in a common row circuit of the plurality of row circuits.
22. The apparatus of claim 20 , further comprising:
means for storing a plurality of micro-ops in a memory; and
means for loading the plurality of micro-ops into the plurality of row circuits in the micro-ops RAM.
23. The apparatus of claim 20 , wherein the means for activating the first row circuit further comprises:
means for activating the first row circuit in a clock cycle.
24. The apparatus of claim 21 , wherein:
the means for activating the first row circuit further comprises:
means for activating the first row circuit in a clock cycle; and
the means for activating the second row circuit further comprises:
means for activating the second row circuit in the clock cycle.