Fan-out semiconductor package

1. A semiconductor package comprising:

a first connection member having a through-hole;

a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip, and filling a portion of the through-hole to separate the semiconductor chip and the first connection member from each other;

a second connection member disposed on the first connection member and the active surface of the semiconductor chip; and

a heat dissipation layer embedded in the encapsulant such that one surface of the heat dissipation layer is exposed,

wherein the second connection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip.

2. The semiconductor package of claim 1 , wherein the heat dissipation layer has a thickness greater than that of a redistribution layer of the first connection member and the redistribution layer of the second connection member.

3. The semiconductor package of claim 1 , further comprising a resin layer disposed on the encapsulant and covering at least portions of the exposed one surface of the heat dissipation layer.

4. The semiconductor package of claim 3 , wherein the resin layer has openings opening at least portions of the exposed one surface of the heat dissipation layer.

5. The semiconductor package of claim 3 , further comprising:

a first opening penetrating the resin layer and the encapsulant exposing a portion of a redistribution layer of the first connection member; and

a second opening penetrating the resin layer exposing a portion of the heat dissipation layer,

wherein the redistribution layer of the first connection member and the heat dissipation layer are disposed on different levels.

6. The semiconductor package of claim 1 , wherein the encapsulant has a thermal conductivity greater than that of an insulating layer of the second connection member.

7. The semiconductor package of claim 6 , wherein the encapsulant and the insulating layer of the second connection member include insulating resins and inorganic fillers, respectively, and a weight percent of the inorganic filler included in the encapsulant is less than that of the inorganic filler included in the insulating layer of the second connection member.

8. The semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer in contact with the second connection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer, opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and

the first and second redistribution layers are electrically connected to the connection pads.

9. The semiconductor package of claim 8 , wherein the first connection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and

the third redistribution layer is electrically connected to the connection pads.

10. The semiconductor package of claim 8 , wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

11. The semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and

the first to third redistribution layers are electrically connected to the connection pads.

12. The semiconductor package of claim 11 , wherein the first connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and

the fourth redistribution layer is electrically connected to the connection pads.

13. The semiconductor package of claim 11 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.

14. The semiconductor package of claim 11 , wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

15. The fan-out semiconductor package of claim 1 , wherein the heat dissipation layer is formed of a metal and is electrically isolated from the redistribution layer of the first connection member.

16. A semiconductor package comprising:

a first connection member having a through-hole;

a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip;

a second connection member disposed on the first connection member and the active surface of the semiconductor chip; and

a heat dissipation layer embedded in the encapsulant such that one surface of the heat dissipation layer is exposed,

wherein the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and

the heat dissipation layer has a thickness greater than that of the redistribution layer of the first connection member and the redistribution layer of the second connection member.

17. The semiconductor package of claim 16 , wherein the heat dissipation layer is formed of a metal and is electrically isolated from the redistribution layer of the first connection member.

18. The semiconductor package of claim 17 , wherein the heat dissipation layer and any of the redistribution layers of the first connection member and the second connection member are disposed on different levels.

19. A semiconductor package comprising:

a first connection member having a through-hole;

a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip;

a second connection member disposed on the first connection member and the active surface of the semiconductor chip;

a heat dissipation layer embedded in the encapsulant such that one surface of the heat dissipation layer is exposed; and

a resin layer disposed on the encapsulant and covering at least portions of the exposed one surface of the heat dissipation layer,

wherein the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip,

a first opening penetrating the resin layer and the encapsulant exposes a portion of the redistribution layer of the first connection member, and

a second opening penetrating the resin layer exposes a portion of the heat dissipation.

20. The semiconductor package of claim 19 , wherein the redistribution layer of the first connection member and the heat dissipation layer are disposed on different levels.