Semiconductor device, semiconductor wafer, memory device, and electronic device
An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.
1. A semiconductor device comprising:
a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, a sixth insulator, a seventh insulator, a conductor, and a semiconductor,
wherein:
the conductor is positioned on a first top surface of the first insulator and on a first bottom surface of the second insulator,
the third insulator is positioned in a region comprising a side surface of the first insulator, a second top surface of the first insulator, a side surface of the conductor, a second bottom surface of the second insulator, and a side surface of the second insulator,
the fourth insulator is in contact with the third insulator,
the fifth insulator is in contact with the fourth insulator,
the semiconductor is in contact with the fifth insulator,
the sixth insulator is in contact with the semiconductor in a region overlapping the conductor with the third insulator, the fourth insulator, and the fifth insulator positioned between the semiconductor and the conductor, and
the seventh insulator is positioned in a region comprising:
the semiconductor in a region overlapping the first insulator and in a region overlapping the second insulator; and
the sixth insulator.
2. The semiconductor device according to claim 1 ,
wherein the fourth insulator is configured to accumulate charge, and
wherein by supply of a potential to the conductor, charge included in the semiconductor is accumulated in the fourth insulator.
3. The semiconductor device according to claim 1 , further comprising a second conductor in contact with the seventh insulator.
4. The semiconductor device according to claim 1 ,
wherein the semiconductor comprises a low-resistance region at and around an interface with the seventh insulator, and
wherein the semiconductor comprises a channel formation region in a region overlapping the conductor.
5. The semiconductor device according to claim 4 ,
wherein the semiconductor comprises a metal oxide,
wherein the low-resistance region comprises a conductive compound, and
wherein the conductive compound comprises a component identical to a component included in the metal oxide and a component identical to a component included in the seventh insulator.
6. The semiconductor device according to claim 4 ,
wherein the semiconductor comprises a metal oxide,
wherein the low-resistance region comprises a conductive compound, and
wherein the conductive compound comprises a component identical to a component included in the metal oxide, and a metal element.
7. A semiconductor wafer comprising:
a plurality of the semiconductor devices according to claim 1 ; and
a region to be subjected to dicing.
8. A memory device comprising:
the semiconductor device according to claim 1 ; and
a peripheral circuit.
9. An electronic device comprising:
the memory device according to claim 8 ; and
a housing.
10. A semiconductor device comprising:
a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, a sixth insulator, a seventh insulator, a conductor, and a semiconductor,
wherein:
the conductor is positioned on a first top surface of the first insulator and on a first bottom surface of the second insulator,
the third insulator is positioned in a region comprising a second top surface of the first insulator, a side surface of the conductor, and a second bottom surface of the second insulator,
the fourth insulator is in contact with the third insulator in a region comprising a region overlapping the conductor, a region overlapping the second top surface of the first insulator, and a region overlapping the second bottom surface of the second insulator,
the fifth insulator is positioned in a region overlapping the side surface of the conductor, a region overlapping a side surface of the first insulator, and a region overlapping a side surface of the second insulator,
the semiconductor is in contact with the fifth insulator,
the sixth insulator is in contact with the semiconductor in a region overlapping the conductor with the third insulator, the fourth insulator, and the fifth insulator positioned between the semiconductor and the conductor, and
the seventh insulator is positioned in a region comprising:
the semiconductor in a region overlapping the first insulator and in a region overlapping the second insulator; and
the sixth insulator.
11. The semiconductor device according to claim 10 ,
wherein the fourth insulator is configured to accumulate charge, and
wherein by supply of a potential to the conductor, charge included in the semiconductor is accumulated in the fourth insulator.
12. The semiconductor device according to claim 10 , further comprising a second conductor in contact with the seventh insulator.
13. The semiconductor device according to claim 10 ,
wherein the semiconductor comprises a low-resistance region at and around an interface with the seventh insulator, and
wherein the semiconductor comprises a channel formation region in a region overlapping the conductor.
14. The semiconductor device according to claim 13 ,
wherein the semiconductor comprises a metal oxide,
wherein the low-resistance region comprises a conductive compound, and
wherein the conductive compound comprises a component identical to a component included in the metal oxide and a component identical to a component included in the seventh insulator.
15. The semiconductor device according to claim 13 ,
wherein the semiconductor comprises a metal oxide,
wherein the low-resistance region comprises a conductive compound, and
wherein the conductive compound comprises a component identical to a component included in the metal oxide, and a metal element.
16. A semiconductor wafer comprising:
a plurality of the semiconductor devices according to claim 10 ; and
a region to be subjected to dicing.
17. A memory device comprising:
the semiconductor device according to claim 10 ; and
a peripheral circuit.
18. An electronic device comprising:
the memory device according to claim 17 ; and
a housing.
19. A semiconductor device comprising:
a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, a sixth insulator, a seventh insulator, a conductor, a first semiconductor, and a second semiconductor,
wherein:
the conductor is positioned on a first top surface of the first insulator and on a first bottom surface of the second insulator,
the second semiconductor is positioned on a side surface of the conductor,
the third insulator is positioned in a region comprising a second top surface of the first insulator, a side surface of the second semiconductor, and a second bottom surface of the second insulator,
the fourth insulator is in contact with the third insulator in a region comprising a region overlapping the conductor, a region overlapping the second top surface of the first insulator, and a region overlapping the second bottom surface of the second insulator,
the fifth insulator is positioned in a region overlapping the side surface of the conductor, a region overlapping the second top surface of the first insulator, and a region overlapping the second bottom surface of the second insulator,
the first semiconductor is positioned in a region overlapping the side surface of the conductor, a region overlapping a side surface of the first insulator, and a region overlapping a side surface of the second insulator,
the sixth insulator is in contact with the first semiconductor in a region overlapping the conductor with the second semiconductor, the third insulator, the fourth insulator, and the fifth insulator positioned between the first semiconductor and the conductor, and
the seventh insulator is positioned in a region comprising:
the first semiconductor in a region overlapping the first insulator and in a region overlapping the second insulator; and
the sixth insulator.
20. The semiconductor device according to claim 19 ,
wherein the fourth insulator is configured to accumulate charge, and
wherein by supply of a potential to the conductor, charge included in the first semiconductor is accumulated in the fourth insulator.
21. The semiconductor device according to claim 19 , further comprising a second conductor in contact with the seventh insulator.
22. The semiconductor device according to claim 19 ,
wherein the first semiconductor comprises a low-resistance region at and around an interface with the seventh insulator, and
wherein the first semiconductor comprises a channel formation region in a region overlapping the conductor.
23. The semiconductor device according to claim 22 ,
wherein the first semiconductor comprises a metal oxide,
wherein the low-resistance region comprises a conductive compound, and
wherein the conductive compound comprises a component identical to a component included in the metal oxide and a component identical to a component included in the seventh insulator.
24. The semiconductor device according to claim 22 ,
wherein the first semiconductor comprises a metal oxide,
wherein the low-resistance region comprises a conductive compound, and
wherein the conductive compound comprises a component identical to a component included in the metal oxide, and a metal element.
25. A semiconductor wafer comprising:
a plurality of the semiconductor devices according to claim 19 ; and
a region to be subjected to dicing.
26. A memory device comprising:
the semiconductor device according to claim 19 ; and
a peripheral circuit.
27. An electronic device comprising:
the memory device according to claim 26 ; and
a housing.
28. A semiconductor device comprising:
a first insulator, a second insulator, a third insulator, a fifth insulator, a sixth insulator, a seventh insulator, a first conductor, a second conductor, and a semiconductor,
wherein:
the first conductor is positioned on a first top surface of the first insulator and on a first bottom surface of the second insulator,
the third insulator is positioned in a region comprising a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface of the second insulator,
the second conductor is in contact with the third insulator in a region overlapping the first conductor,
the fifth insulator is positioned in a region comprising:
the third insulator in a region overlapping the second top surface of the first insulator and in a region overlapping the second bottom surface of the second insulator; and
the second conductor,
the semiconductor is positioned in a region overlapping the side surface of the first conductor, a region overlapping a side surface of the first insulator, and a region overlapping a side surface of the second insulator,
the sixth insulator is in contact with the semiconductor in a region overlapping the first conductor with the third insulator, the second conductor, and the fifth insulator positioned between the semiconductor and the first conductor, and
the seventh insulator is positioned in a region comprising:
the semiconductor in a region overlapping the first insulator and in a region overlapping the second insulator; and
the sixth insulator.
29. The semiconductor device according to claim 28 ,
wherein the second conductor is configured to accumulate charge, and
wherein by supply of a potential to the first conductor, charge included in the semiconductor is accumulated in the second conductor.
30. The semiconductor device according to claim 28 , further comprising a third conductor in contact with the seventh insulator.
31. The semiconductor device according to claim 28 ,
wherein the semiconductor comprises a low-resistance region at and around an interface with the seventh insulator, and
wherein the semiconductor comprises a channel formation region in a region overlapping the first conductor.
32. The semiconductor device according to claim 31 ,
wherein the semiconductor comprises a metal oxide,
wherein the low-resistance region comprises a conductive compound, and
wherein the conductive compound comprises a component identical to a component included in the metal oxide and a component identical to a component included in the seventh insulator.
33. The semiconductor device according to claim 31 ,
wherein the semiconductor comprises a metal oxide,
wherein the low-resistance region comprises a conductive compound, and
wherein the conductive compound comprises a component identical to a component included in the metal oxide, and a metal element.
34. A semiconductor wafer comprising:
a plurality of the semiconductor devices according to claim 28 ; and
a region to be subjected to dicing.
35. A memory device comprising:
the semiconductor device according to claim 28 ; and
a peripheral circuit.
36. An electronic device comprising:
the memory device according to claim 35 ; and
a housing.