Reducing uncorrectable errors based on a history of correctable errors
View Patent ↗In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.
1. A system comprising:
a memory having computer-readable instructions; and
one or more processors for executing the computer-readable instructions, the computer-readable instructions comprising:
maintaining two or more error indicators for correctable errors occurring at two or more memory components, wherein each of the two or more error indicators is associated with a corresponding memory component of the two or more memory components;
detecting a correctable error occurring during a first memory fetch operation at a first memory component of the two or more memory components;
setting a first error indicator, of the two or more error indicators, corresponding to the first memory component, responsive to the correctable error at the first memory component;
detecting an uncorrectable error during a second memory fetch operation at a second memory component;
detecting that the first error indicator is set; and
taking offline at least one of the two or more memory components, responsive to the uncorrectable error and based on statuses of the two or more memory indicators, wherein the taking offline comprises:
taking offline the first memory component corresponding to the first error indicator, responsive to the first error indicator being set and responsive to the uncorrectable error occurring during the second memory fetch operation at the second memory component.
2. The system of claim 1 , wherein:
the two or more error indicators are implemented with two or more error counters, each of the two or more error indicators being implemented with a corresponding error counter of the two or more error counters;
setting the first error indicator comprises incrementing a first error counter corresponding to the first error indicator to a value that is at least a threshold count; and
detecting that the first error indicator is set comprises detecting that the first error counter has a value of at least the threshold count.
3. The system of claim 2 , the computer-readable instructions further comprising:
incrementing an interval counter responsive to at least one of each memory fetch operation and each elapsed time interval; and
decrementing each of the two or more error counters when an overflow event occurs on the interval counter.
4. The system of claim 2 , the computer-readable instructions further comprising:
determining that each of the two or more error counters other than the first error counter has a value that differs from the first error counter by at least a threshold difference;
wherein taking offline the first memory component is further responsive to determining that each of the two or more error counters other than the first error counter has a value that differs from the first error counter by at least a threshold difference.
5. The system of claim 1 , wherein taking offline the first memory component occurs outside of a memory scrub.
6. The system of claim 1 , wherein at least one of the two or more memory components is a memory channel in a redundant array of independent memory system.
7. The system of claim 1 , wherein at least one of the two or more memory components is at least one of a memory chip and a memory rank.
8. A computer-program product for marking memory components, the computer-program product comprising a computer-readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
maintaining two or more error indicators for correctable errors occurring at two or more memory components, wherein each of the two or more error indicators is associated with a corresponding memory component of the two or more memory components;
detecting a correctable error occurring during a first memory fetch operation at a first memory component of the two or more memory components;
setting a first error indicator, of the two or more error indicators, corresponding to the first memory component, responsive to the correctable error at the first memory component;
detecting an uncorrectable error during a second memory fetch operation at a second memory component;
detecting that the first error indicator is set; and
taking offline at least one of the two or more memory components, responsive to the uncorrectable error and based on statuses of the two or more memory indicators, wherein the taking offline comprises:
taking offline the first memory component corresponding to the first error indicator, responsive to the first error indicator being set and responsive to the uncorrectable error occurring during the second memory fetch operation at the second memory component.
9. The computer-program product of claim 8 , wherein:
the two or more error indicators are implemented with two or more error counters, each of the two or more error indicators being implemented with a corresponding error counter of the two or more error counters;
setting the first error indicator comprises incrementing a first error counter corresponding to the first error indicator to a value that is at least a threshold count; and
detecting that the first error indicator is set comprises detecting that the first error counter has a value of at least the threshold count.
10. The computer-program product of claim 9 , the method further comprising:
incrementing an interval counter responsive to at least one of each memory fetch operation and each elapsed time interval; and
decrementing each of the two or more error counters when an overflow event occurs on the interval counter.
11. The computer-program product of claim 9 , the method further comprising:
determining that each of the two or more error counters other than the first error counter has a value that differs from the first error counter by at least a threshold difference;
wherein taking offline the first memory component is further responsive to determining that each of the two or more error counters other than the first error counter has a value that differs from the first error counter by at least a threshold difference.
12. The computer-program product of claim 8 , wherein taking offline the first memory component occurs outside of a memory scrub.
13. The computer-program product of claim 8 , wherein at least one of the two or more memory components is a memory channel in a redundant array of independent memory system.
14. The computer-program product of claim 8 , wherein at least one of the two or more memory components is at least one of a memory chip and a memory rank.