Method of manufacturing a CMOS transistor
A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
1. A method to manufacture a complementary metal-oxide-semiconductor (CMOS) transistor, the method comprising:
forming a gate insulating film on a semiconductor substrate;
forming a conductive film on the gate insulating film;
forming a first gate electrode pattern and a second gate electrode pattern, by patterning of the conductive film;
performing a first ion injection process into the semiconductor substrate to form an n-type well region in the semiconductor substrate, wherein the performing of the first ion injection process comprises performing ion injection through the second gate electrode pattern;
forming a p-type lightly doped drain (LDD) region in the n-type well region;
performing a second ion injection process into the semiconductor substrate to form a p-type well region in the semiconductor substrate, wherein the performing of the second ion injection process comprises performing ion injection through the first gate electrode pattern;
forming an n-type LDD region in the p-type well region;
forming sidewall spacers at sidewalls of each of the first and second gate electrode patterns;
forming an n-type source region and an n-type drain region in the p-type well region; and
forming a p-type source region and a p-type drain region in the n-type well region,
wherein the n-type well region and the p-type LDD region are formed using a first photoresist pattern, and the p-type well region and the n-type LDD region are formed using a second photoresist pattern.
2. The method of claim 1 , further comprising forming separation films in the semiconductor substrate before the forming of the gate insulating film.
3. The method of claim 2 , wherein the performing of the first ion injection process further comprises:
performing ion injection such that the n-type well region is formed deeper than the separation films, and such that a depth of the n-type well region below the second gate electrode pattern is shallower than a depth of the n-type well region below the separation films.
4. The method of claim 2 , wherein the performing of the second injection process further comprises:
performing ion injection such that the p-type well region is formed deeper than the separation films, and such that a depth of the p-type well region below the first gate electrode pattern is shallower than a depth of the p-type well region below the separation films.
5. The method of claim 1 , further comprising:
forming an n-type threshold voltage adjustment area below the second gate electrode pattern after the performing of the first ion injection process, wherein the forming of the n-type threshold voltage adjustment area comprises performing n-type ion injection into the semiconductor substrate through the second gate electrode pattern.
6. The method of claim 1 , further comprising:
forming a p-type threshold voltage adjustment area below the first gate electrode pattern after the performing of the second ion injection process, wherein the forming of the p-type threshold voltage adjustment area comprises performing p-type ion injection into the semiconductor substrate through the first gate electrode pattern.
7. A method to manufacture a complementary metal-oxide-semiconductor (CMOS) transistor, the method comprising:
forming a gate insulating film on a semiconductor substrate;
forming a conductive film on the gate insulating film;
forming a first gate electrode pattern and a second gate electrode pattern by patterning of the conductive film;
performing a first ion injection process into the semiconductor substrate to form an n-type well region in the semiconductor substrate using a first photoresist pattern, wherein the performing of the first ion injection process comprises performing ion injection through the second gate electrode pattern;
forming a p-type lightly doped drain (LDD) region in the n-type well region using the first photoresist pattern;
performing a second ion injection process into the semiconductor substrate to form a p-type well region in the semiconductor substrate using a second photoresist pattern, wherein the performing of the second ion injection process comprises performing ion injection through the first gate electrode pattern;
forming an n-type LDD region in the p-type well region using the second photoresist pattern;
forming an n-type source region and an n-type drain region in the p-type well region; and
forming a p-type source region and a p-type drain region in the n-type well region.
8. A method to manufacture a complementary metal-oxide-semiconductor (CMOS) transistor, the method comprising:
forming a gate insulating film on a semiconductor substrate;
forming a conductive film on the gate insulating film;
forming a first gate electrode pattern and a second gate electrode pattern by patterning the conductive film;
performing a first ion injection process into the semiconductor substrate to form an n-type well region in the semiconductor substrate using a first photoresist pattern, wherein the performing of the first ion injection process comprises performing ion injection through the second gate electrode pattern;
forming a p-type lightly doped drain (LDD) region in the n-type well region using the first photoresist pattern;
performing a second ion injection process into the semiconductor substrate to form a p-type well region in the semiconductor substrate using a second photoresist pattern, wherein the performing of the second ion injection process comprises performing ion injection through the first gate electrode pattern; and
forming an n-type LDD region in the p-type well region using the second photoresist pattern.
9. The method of claim 1 , wherein a depth of the p-type well region below the first gate electrode pattern is shallower than a depth of the p-type well region below the n-type source region.
10. The method of claim 7 , wherein a depth of the p-type well region below the first gate electrode pattern is shallower than a depth of the p-type well region below the n-type source region.
11. The method of claim 8 , further comprising:
forming an n-type source region in the p-type well region,
wherein a depth of the p-type well region below the first gate electrode pattern is shallower than a depth of the p-type well region below the n-type source region.
12. The method of claim 7 , further comprising:
forming a separation film in the semiconductor substrate,
wherein a depth of the p-type well region below the first gate electrode pattern is shallower than a depth of the p-type well region below the separation film.
13. The method of claim 8 , further comprising:
forming a separation film in the semiconductor substrate,
wherein a depth of the p-type well region below the first gate electrode pattern is shallower than a depth of the p-type well region below the separation film.
14. The method of claim 1 , further comprising:
forming an n-type halo region in the n-type well region with the first photoresist pattern; and
forming an p-type halo region in the p-type well region with the second photoresist pattern.
15. The method of claim 7 , further comprising:
forming an n-type halo region in the n-type well region with the first photoresist pattern; and
forming an p-type halo region in the p-type well region with the second photoresist pattern.
16. The method of claim 8 , further comprising:
forming an n-type halo region in the n-type well region with the first photoresist pattern; and
forming an p-type halo region in the p-type well region with the second photoresist pattern.