Method of forming three-dimensional integrated circuit having ESD protection circuit
View Patent ↗A method (of forming an integrated circuit) includes: forming a first diode on a first substrate of two or more stacked substrates, the first substrate having a first predetermined doping type; forming a second diode on a second substrate of the two or more stacked substrates, the second substrate being formed on the first substrate, and the second substrate having the first predetermined doping type; and forming conductive paths electrically connecting the first diode 3A and the second diode between a circuit and a first common ground rail, the first diode and the second diode being connected in parallel and having opposite polarities.
1. A method of forming an integrated circuit, the method comprising:
forming a first diode on a first substrate of two or more stacked substrates, the first substrate having a first predetermined doping type;
forming a second diode on a second substrate of the two or more stacked substrates, the second substrate being formed over the first substrate, and the second substrate having the first predetermined doping type; and
forming conductive paths electrically connecting the first diode and the second diode between a circuit and a first common ground rail, the first diode and the second diode being connected in parallel and having opposite polarities; and
forming a second common ground rail electrically connected to the first substrate and the second substrate.
2. The method of claim 1 , wherein:
the first predetermined doping type is a P-type doping.
3. The method of claim 2 , further comprising:
electrically connecting the first common ground rail and the second common ground rail.
4. The method of claim 1 , wherein:
a second predetermined doping type is an N-type doping; and
the method further comprises:
forming a first isolation structure in a third substrate, the first isolation structure surrounding a third diode that is in the third substrate; and
forming a second isolation structure in a fourth substrate, the second isolation structure surrounding a fourth diode that is in the fourth substrate.
5. The method of claim 1 , wherein the forming conductive paths electrically connecting the first diode and the second diode between the circuit and the first common ground rail includes:
forming a first intermediate ground rail;
connecting the circuit to the first intermediate ground rail; and
connecting the first diode and the second diode to the first intermediate ground rail.
6. The method of claim 1 , wherein
the two or more stacked substrates include:
a third substrate having a second predetermined doping type; and
a fourth substrate formed over the second substrate, the fourth substrate having the second predetermined doping type; and
the method further comprises:
forming a third diode on the third substrate; and
forming a fourth diode on the fourth substrate.
7. The method of claim 6 , wherein:
the circuit to which the first diode and the second diode are connected is a first circuit; and
the method further comprises:
forming conductive paths electrically connecting the third diode and the fourth diode between a second circuit and the first common ground rail, the third diode and the fourth diode being connected in parallel and having opposite polarities.
8. The method of claim 7 , wherein the forming conductive paths electrically connecting the third diode and the fourth diode between the second circuit and the first common ground rail includes:
forming a first intermediate ground rail;
connecting the second circuit to the first intermediate ground rail; and
connecting the third diode and the fourth diode to the first intermediate ground rail.
9. A method of forming an integrated circuit, the method comprising:
forming a first diode on a first substrate of two or more stacked substrates, the first diode having a first predetermined conductivity type;
forming a second diode on a second substrate of the two or more stacked substrates, the second substrate being formed over the first substrate, and the second diode having the first predetermined conductivity type; and
forming conductive paths electrically connecting the first diode and the second diode between a circuit and a first common ground rail, the first diode and the second diode being connected in parallel and having opposite polarities; and
forming a second common ground rail electrically connected to the first substrate and the second substrate.
10. The method of claim 9 , further comprising:
electrically connecting the first common ground rail and the second common ground rail; and
wherein the first predetermined conductivity type is a P-type.
11. The method of claim 9 , wherein:
the method further comprises:
forming a first isolation structure in a third substrate, the first isolation structure surrounding a third diode.
12. The method of claim 9 , wherein the forming conductive paths electrically connecting the first diode and the second diode between the circuit and the first common ground rail includes:
forming a first intermediate ground rail;
connecting the circuit and to the first intermediate ground rail; and
connecting the first diode and the second diode to the first intermediate ground rail.
13. The method of claim 9 , wherein
the two or more stacked substrates include:
a third substrate formed over the second substrate, the third substrate having a second predetermined doping type; and
a fourth substrate formed below the first substrate, the fourth substrate having the second predetermined doping type; and
the method further comprises:
forming a third diode on the third substrate; and
forming a fourth diode on the fourth substrate.
14. The method of claim 13 , wherein:
the circuit to which the first diode and the second diode are connected is a first circuit; and
the method further comprises:
forming conductive paths electrically connecting the third diode and the fourth diode between a second circuit and the first common ground rail, the third diode and the fourth diode being connected in parallel and having opposite polarities.
15. The method of claim 6 , wherein:
the third substrate is located on the first substrate;
the fourth substrate is located on the third substrate; and
the second substrate is located on the fourth substrate.
16. A method of forming an integrated circuit, the method comprising:
forming a stack of first, second, third and fourth substrates having a same predetermined doping type;
forming a first diode on the first substrate, the first diode having a first predetermined conductivity type;
forming a second diode on the fourth substrate, the second diode having the first predetermined conductivity type;
forming a third diode on the second substrate, the third diode having a second predetermined conductivity type;
forming a fourth diode on the third substrate, the fourth diode having the second predetermined conductivity type; and
forming conductive paths electrically connecting a first pair of the first, second, third and fourth diodes between a circuit and a first common ground rail, the first pair being connected in parallel and having opposite polarities; and
forming a second common ground rail electrically connected to a first pair of the first, second, third and fourth substrates.
17. The method of claim 16 , wherein:
the first pair of the first, second, third and fourth diodes includes the first diode and the second diode.
18. The method of claim 17 , wherein:
the method further comprises:
forming conductive paths electrically connecting a second pair including the third and fourth diodes between a second circuit and the first common ground rail, the second pair being connected in parallel and having opposite polarities.
19. The method of claim 1 , wherein:
portions of the conductive paths are embedded in interconnect structures formed correspondingly over the two or more stacked substrates.
20. The method of claim 9 , wherein:
portions of the conductive paths are embedded in interconnect structures formed correspondingly over the two or more stacked substrates.