IP Library Granted Patent US 10,891,061
Granted Patent B2
US 10,891,061 · App. 16/052,880 · Granted Jan 12, 2021

Electronic device, computer system, and control method

Inventors: Daisuke Iwai (Yokohama, JP); Kenichiro Yoshii (Bunkyo, JP); Tetsuya Sunata (Yokohama, JP)
Assignee: Toshiba Memory Corporation
G06F3/0625G06F3/0659G06F3/0679
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Quick Facts
Patent No.
US 10,891,061
App. No.
16/052,880
Granted
Jan 12, 2021
Kind
B2
Abstract

According to one embodiment, an electronic device connectable to a host via an interface includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory and capable of processing commands issued by the host in parallel. When the electronic device is connected to the host, the controller determines, when one or more commands to be processed by one or more deadline times, respectively, are issued by the host, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times. The controller performs processing corresponding to the one or more commands in accordance with the scheduling.

Claims (72)

1. An electronic device comprising:

a memory; and

a processor configured to execute a program stored in the memory, wherein

the processor is configured to:

determine, when issuing a first command to a storage device is requested, a deadline time by which the first command is to be processed, wherein the storage device is capable of processing commands issued by the processor; and

issue the first command for which the deadline time is designated, to the storage device,

wherein the processor is configured to:

determine, when at least a portion of data constituting a file is written into the storage device while the file is being downloaded to the electronic device via a network, a first deadline time by which a write command for writing at least the portion of data is to be processed based on a speed at which the file is downloaded; and

issue the write command for which the first deadline time is designated to the storage device.

2. The electronic device of claim 1 , wherein

the processor is configured to:

issue a first command for which a first deadline time is designated to a first storage device having first performance and a second command for which a second deadline time is designated to a second storage device having second performance lower than the first performance, wherein the second deadline time is longer than the first deadline time; and

issue an abort command for canceling the second command to the second storage device when processing of the first command by the first storage device is completed before processing of the second command by the second storage device is completed.

3. The electronic device of claim 1 , wherein

the processor is further configured to estimate a wear degree of the storage device based on a time when processing of the first command by the storage device is completed.

4. The electronic device of claim 1 , wherein

the processor stores the issued first command in a queue, and

the stored first command is fetched from the queue in accordance with scheduling determined based on the deadline time.

5. The electronic device of claim 1 , wherein

the storage device comprises:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and capable of processing the commands in parallel.

6. The electronic device of claim 5 , wherein

the controller is configured to determine, when one or more commands to be processed by one or more deadline times, respectively, are issued, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times.

7. A computer system comprising a storage device and a host, wherein

the host comprises:

a memory; and

a processor configured to execute a program stored in the memory, the processor is configured to:

determine, when issuing a first command to the storage device is requested, a deadline time by which the first command is to be processed; and

issue the first command for which the deadline time is designated, to the storage device,

the storage device is capable of processing commands issued by the processor, and the processor is configured to:

determine, when at least a portion of data constituting a file is written into the storage device while the file is being downloaded to the host via a network, a first deadline time by which a write command for writing at least the portion of data is to be processed based on a speed at which the file is downloaded; and

issue the write command for which the first deadline time is designated to the storage device.

8. The computer system of claim 7 , wherein

the processor stores the issued first command in a queue, and

the stored first command is fetched from the queue in accordance with scheduling determined based on the deadline time.

9. The computer system of claim 7 , wherein

the processor is configured to:

issue a first command for which a first deadline time is designated to a first storage device having first performance and a second command for which a second deadline time is designated to a second storage device having second performance lower than the first performance, wherein the second deadline time is longer than the first deadline time; and

issue an abort command for canceling the second command to the second storage device when processing of the first command by the first storage device is completed before processing of the second command by the second storage device is completed.

10. The computer system of claim 7 , wherein

the processor is further configured to estimate a wear degree of the storage device based on a time when processing of the first command by the storage device is completed.

11. The computer system of claim 7 , wherein

the storage device comprises:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and capable of processing the commands in parallel.

12. The computer system of claim 11 , wherein

the controller is configured to determine, when one or more commands to be processed by one or more deadline times, respectively, are issued, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times.

13. An electronic device comprising:

a memory; and

a processor configured to execute a program stored in the memory, wherein

the processor is configured to:

determine, when issuing a first command to a storage device is requested, a deadline time by which the first command is to be processed, wherein the storage device is capable of processing commands issued by the processor; and

issue the first command for which the deadline time is designated to the storage device,

wherein the processor is configured to:

determine, when data stored in a first storage device is copied to a second storage device, a first deadline time by which a read command for reading the data is to be processed based on read performance of the first storage device and write performance of the second storage device; and

issue the read command for which the first deadline time is designated to the first storage device.

14. The electronic device of claim 13 , wherein

the processor stores the issued first command in a queue, and

the stored first command is fetched from the queue in accordance with scheduling determined based on the deadline time.

15. The electronic device of claim 13 , wherein

the processor is configured to:

issue a first command for which a first deadline time is designated to a first storage device having first performance and a second command for which a second deadline time is designated to a second storage device having second performance lower than the first performance, wherein the second deadline time is longer than the first deadline time; and

issue an abort command for canceling the second command to the second storage device when processing of the first command by the first storage device is completed before processing of the second command by the second storage device is completed.

16. The electronic device of claim 13 , wherein

the processor is further configured to estimate a wear degree of the storage device based on a time when processing of the first command by the storage device is completed.

17. The electronic device of claim 13 , wherein

the storage device comprises:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and capable of processing the commands in parallel.

18. The electronic device of claim 17 , wherein

the controller is configured to determine, when one or more commands to be processed by one or more deadline times, respectively, are issued, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Feb 4, 2022
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058957/0124 →
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
MERGER Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 058946/0675 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2018
From: IWAI, DAISUKE; YOSHII, KENICHIRO; SUNATA, TETSUYA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 046536/0852 →
Cited By (4)
US 12,541,451 US 12,619,380 US 12,645,397 US 12,711,057