Granted Patent B2

US 12,645,397 · App. 18/227,899 · Granted Jun 2, 2026

Inventors: Daniel Lee Helmick (Thornton, CO); Robert Wayne Moss (Fort Collins, CO); Michael Allison (Longmont, CO); Sumanth Jannyavula Venkata (Pleasanton, CA); Judith Rose Brock (Berkeley, CA)

Assignee: SAMSUNG ELECTRONICS CO., LTD.

G06F3/0659G06F3/0679G06F3/0604

Abstract

Claims (48)

1 . A memory, comprising:

a first data structure stored in the memory, the first data structure including a first field to store a first data relating to a command;

a second data structure stored in the memory, the second data structure including a second field to store a second data relating to the command;

a first queue stored in the memory, the first queue including the first data structure, the first queue including a first relative ordering of the first data structure and a third data structure storing a third data relating to a second command; and

a second queue stored in the memory, the second queue including the second data structure, the second queue including a second relative ordering of the second data structure and a fourth data structure storing a fourth data relating to the second command,

wherein the first queue is a first submission queue and the second queue is a second submission queue, or the first queue is a first completion queue and the second queue is a second completion queue

wherein the second relative ordering parallels the first relative ordering, and

wherein a controller is configured to process the command based at least in part on the first data relating to the command and the second data relating to the command.

2 . The memory according to claim 1 , wherein:

the first queue includes a number of entries; and

the second queue includes the number of entries.

3 . The memory according to claim 2 , wherein:

the first data structure is located at a position in the first queue; and

the second data structure is located at a same position in the second queue.

4 . The memory according to claim 1 , wherein:

the first queue includes a first number of entries; and

the second queue includes a second number of entries,

wherein the second number of entries is less than the first number of entries.

5 . The memory according to claim 4 , wherein the first data structure includes a third field to store an identifier of the second data structure.

6 . The memory according to claim 4 , wherein the second data structure includes a phase value.

7 . A method, comprising:

establishing a first data structure by a processor, the first data structure including a first field storing a first data relating to a command;

establishing a second data structure by the processor, the second data structure including a second field storing a second data related to the command;

storing the first data structure in a first queue in a memory by the processor, the first queue including a first relative ordering of the first data structure and a third data structure storing a third data relating to a second command; and

storing the second data structure in a second queue in the memory by the processor, the second queue including a second relative ordering of the second data structure and a fourth data structure storing a fourth data relating to the second command,

wherein the first queue is a first submission queue and the second queue is a second submission queue, or the first queue is a first completion queue and the second queue is a second completion queue, and

wherein the second relative ordering parallels the first relative ordering.

8 . The method according to claim 7 , wherein establishing the first data structure by the processor includes storing a value in a third field in the first data structure to indicate the presence of the second data structure in the memory.

9 . The method according to claim 7 , wherein:

establishing the first data structure by the processor includes storing an operation code (opcode) or a command identifier in a third field in the first data structure; and

establishing the second data structure by the processor includes storing the opcode or the command identifier in a fourth field in the second data structure.

10 . The method according to claim 7 , wherein:

the first queue includes a number of entries; and

the second queue includes the number of entries.

11 . The method according to claim 10 , wherein:

the first data structure is located at a position in the first queue; and

the second data structure is located at a same position in the second queue.

12 . The method according to claim 7 , wherein:

the first queue includes a first number of entries; and

the second queue includes a second number of entries,

wherein the second number of entries is less than the first number of entries.

13 . The method according to claim 12 , wherein establishing a first data structure by a processor includes storing an identifier of the second data structure in a third field in the first data structure.

14 . The method according to claim 12 , wherein the second data structure includes a phase value.

15 . The method according to claim 7 , wherein:

the method further comprises:

requesting a format for the second data structure from a storage device by the processor; and

receiving the format for the second data structure from the storage device by the processor; and

establishing the second data structure by the processor includes establishing the second data structure by the processor based at least in part on the format for the second data structure received from the storage device by the processor.

Continuity (3)

References Cited (86)