Out of order memory command fetching

1. A memory device, comprising:

physical memory device resources for executing memory commands in the memory device;

a command fetching engine configured to:

determine availability of the physical memory device resources for executing memory commands in the memory device;

fetch memory commands from a submission queue of a host computing system for execution in the memory device, wherein fetching the memory commands comprises:

examining respective memory commands within the submission queue to determine whether physical memory device resources required for execution of the respective commands in the memory device are satisfied by the determined availability of the physical memory resources in the memory device, prior to fetching the respective commands from the submission queue, and

fetching selected memory commands from the submission queue in response to determining that the physical memory device resources required for execution of the selected commands are satisfied by the determined availability of the physical memory device resources in the memory device; and

identify physical memory device resources required for execution of a first memory command by:

partially fetching the first memory command from the submission queue of the host computing system, wherein partially fetching the first memory command comprises transferring a first portion of the first memory command to the memory device without transferring a second portion of the first memory command to the memory device; and

parsing the first portion of the first memory command at the memory device; and

a memory controller configured to execute the fetched memory commands by use of the physical memory device resources in the memory device.

2. The memory device-of claim 1 , wherein the command fetching engine comprises a read module configured to:

identify physical memory device resources that are currently available for executing read commands in the memory device;

examine respective read commands in the submission queue to identify physical memory device resources required for execution of the respective read commands in the memory device; and

select a read command to fetch from the submission queue in response to matching required physical memory resources of the selected read command to one or more of the physical memory device resources identified as being currently available for executing read commands in the memory device.

3. The memory device-of claim 1 , wherein the command fetching engine comprises a write module configured to:

identify physical memory device resources that are currently available for executing write commands in the memory device;

respective write commands in the submission queue to identify physical memory device resources required for execution of the respective write commands in the memory device; and

select a write command to fetch from the submission queue in response to determining that the required physical memory device resources of the selected write command correspond to one or more of the physical memory device resources of the memory device identified as being currently available for executing write commands in the memory device.

4. The memory device-of claim 1 , wherein:

the determined availability of the physical memory device resources of the memory device indicates that each of a first memory plane and a second memory plane of the memory device are currently available for executing memory commands in the memory device; and

fetching the memory commands from the submission queue further comprises:

selecting a first memory command to fetch from the submission queue in response to determining that the required physical memory device resources of the first memory command correspond to the first memory plane, and

selecting a second memory command to fetch from the submission queue in response to determining that the required physical memory device resources of the second memory command correspond to the second memory plane.

5. The memory device of claim 4 , wherein the command fetching engine is further configured to:

merge the first memory command and the second memory command into a single multiplane memory command for execution on both of the first memory plane and the second memory plane; and

fetch the single multiplane memory command for execution in the memory device.

6. The memory device of claim 5 , wherein the first memory command comprises a first single-plane read command, the second memory command comprises a second single-plane read command, and the single multiplane memory command comprises a single multiplane read command.

7. The memory device of claim 5 , wherein the first memory command comprises a first single-plane write command, the second memory command comprises a second single-plane write command, and the single multiplane memory command comprises a single multiplane write command.

8. The memory device of claim 5 , wherein the first memory command comprises a first admin command, the second memory command comprises a second admin command, and the single multiplane memory command comprises a single multiplane admin command.

9. The memory device of claim 4 , wherein the command fetching engine determines that the first memory command corresponds to the first memory plane in response to translating a logical block address of the first memory command to a physical block address within the first memory plane.

10. The memory device-of claim 1 , wherein:

the determined availability of the physical memory device resources in the memory device identify a memory die of a plurality of memory die that is currently available for executing memory commands in the memory device, and

fetching the memory commands from the submission queue further comprises:

fetching a first memory command from the submission queue in response to determining that a logical address associated with the first memory command corresponds to a physical address of the identified memory die, and

deferring fetching of a second memory command from the submission queue in response to determining that a logical address associated with the second memory command corresponds to a physical address of a memory die other than the identified memory die.

11. The memory device-of claim 1 , wherein:

the command fetching engine is further configured to identify a memory die that is currently being used to implement a low-latency operation in the memory device and a memory die that is currently being used to implement a high-latency operation in the memory device; and

fetching the memory commands from the submission queue further comprises:

fetching a first memory command to the memory device from the submission queue in response to determining that the first memory command corresponds to the memory die that is currently implementing the low-latency operation,

wherein a second memory command that corresponds to the memory die that is currently implementing the high-latency operation and is ordered before the first memory command in the submission queue is fetched from the submission queue after fetching the first memory command.

12. A memory device, comprising:

physical memory device resources for executing memory commands in the memory device;

a command fetching engine configured to:

determine availability of the physical memory device resources for executing memory commands in the memory device; and

fetch memory commands from a submission queue of a host computing system for execution in the memory device, wherein fetching the memory commands comprises:

examining respective memory commands within the submission queue to determine whether physical memory device resources required for execution of the respective commands in the memory device are satisfied by the determined availability of the physical memory resources in the memory device, prior to fetching the respective commands from the submission queue, and

fetching selected memory commands from the submission queue in response to determining that the physical memory device resources required for execution of the selected commands are satisfied by the determined availability of the physical memory device resources in the memory device, wherein:

the command fetching engine determines a current power consumption of the memory device based on one or more memory commands being executed in the memory device; and

fetching the memory commands from the submission queue further comprises:

determining power requirements of the respective memory commands within the submission queue, and

selecting memory commands to fetch from the submission queue based on the determined power requirements of the respective commands and the current power consumption of the memory device; and

a memory controller configured to execute the fetched memory commands by use of the physical memory device resources in the memory device.

13. A memory device, comprising:

physical memory device resources for executing memory commands in the memory device;

a command fetching engine configured to:

determine availability of the physical memory device resources for executing memory commands in the memory device; and

fetch memory commands from a submission queue of a host computing system for execution in the memory device, wherein fetching the memory commands comprises:

examining respective memory commands within the submission queue to determine whether physical memory device resources required for execution of the respective commands in the memory device are satisfied by the determined availability of the physical memory resources in the memory device, prior to fetching the respective commands from the submission queue, and

fetching selected memory commands from the submission queue in response to determining that the physical memory device resources required for execution of the selected commands are satisfied by the determined availability of the physical memory device resources in the memory device, wherein:

the determined availability of the physical memory device resources of the memory device indicates that the memory device is currently executing one or more memory commands associated with high power consumption; and

fetching the memory commands from the submission queue further comprises:

selecting a first memory command to fetch from the submission queue in response to determining that the first memory command is one of a read command and an admin command, and

preventing a second memory command from being fetched from the submission queue in response to determining that the second memory command is one of a write command and an erase command; and

a memory controller configured to execute the fetched memory commands by use of the physical memory device resources in the memory device.

14. The memory device-of claim 1 , wherein fetching the memory commands from the submission queue further comprises:

identifying two or more memory commands within the submission queue that correspond to one or more of a same memory die and a same memory plane;

combining the two or more memory commands into a single memory command prior to fetching the two or more memory commands from the submission queue; and

transferring the single memory command to the memory device.

15. The memory device of claim 14 , wherein the single memory command comprises one of a read cached page command and a write cached page command.

16. A memory system, comprising:

a memory array comprising a plurality of memory die;

a translation engine configured to convert logical addresses to corresponding physical addresses within respective memory die of the memory array;

a command fetching engine communicatively coupled to a host queue through a bus, the command fetching engine configured to:

identify idle memory die of the memory array that are currently available for memory command execution,

partially fetch memory commands from the host queue, wherein partially fetching a memory command comprises accessing designated portions of respective memory commands through the bus without accessing one or more other portions of the respective memory commands,

map the respective memory commands to respective memory die of the memory array using the translation engine and the designated portions of the partially fetched memory commands,

identify memory commands within the host queue that map to idle memory die of the memory array that are currently available for memory command execution, and

fetch one or more of the identified memory commands from the host queue; and

a controller configured to execute the memory commands fetched from the host queue using one or more of the memory die.