IP Library Granted Patent US 10,242,891
Granted Patent B2
US 10,242,891 · App. 16/056,792 · Granted Mar 26, 2019

Apparatus and method for securing components of an integrated circuit

Inventors: Jean-Philippe Fricker (Los Altos, CA); Frank Jun (Los Altos, CA); Paul Kennedy (Los Altos, CA)
Assignee: Cerebras Systems Inc.
H01L21/67121H01L25/50
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Quick Facts
Patent No.
US 10,242,891
App. No.
16/056,792
Granted
Mar 26, 2019
Kind
B2
Abstract

Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.

Claims (41)

1. A method of securing an integrated circuit assembly, the method comprising:

arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly;

applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly;

after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and

terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.

2. The method according to claim 1 , wherein

at least one layer component of the integrated circuit assembly comprises a semiconductor substrate having:

a plurality of die formed with the semiconductor substrate;

a circuit layer formed at each of the plurality of die; and

a plurality of inter-die connections that communicatively connect disparate die formed with the substrate, wherein each of the plurality of inter-die connections extends between each pair of adjacent die of the plurality of die.

3. The method according to claim 2 , wherein

the plurality of layer components further comprising:

an electronic circuit substrate; and

an elastomeric connector arranged between the semiconductor substrate and the electronic circuit substrate.

4. The method according to claim 1 , wherein

the mechanical compression load is applied by a clamping assembly, the clamping assembly comprising:

a load application component that applies the mechanical compression load against the plurality of layer components of the integrated circuit assembly;

a mechanical securing component that fastens each of the plurality of securing elements within the integrated circuit assembly.

5. The method according to claim 1 , wherein:

each of the plurality of securing elements comprises an elastic member arranged between an abutment portion of each securing element and a surface of one of the plurality of layers of the integrated circuit assembly,

the elastic member absorbs expansion forces and contraction forces of the one or more of the plurality of layer components of the integrated circuit assembly.

6. The method according to claim 1 , wherein:

the securing element comprises a plurality of elastic members disposed between a surface of abutment portion of the securing element and a surface of a layer component comprising a backing element of the integrated circuit assembly;

fastening the securing element into the integrated circuit assembly causes the surface of the abutment portion to come into contact with the plurality of the elastic members and compress the plurality of elastic members from a first uncompressed position to a second compressed position.

7. The method according to claim 1 , further comprising:

arranging a plurality of fastening members within or at a surface of an electronic circuit substrate of the integrated circuit assembly, wherein fastening the plurality of securing elements includes fastening one end of each of the plurality of securing element with one fastening member of the plurality of fastening members.

8. The method according to claim 1 , wherein

fastening the plurality of securing elements is triggered in response to achieving a desired mechanical compression load.

9. The method according to claim 1 , wherein

fastening the plurality of securing elements includes fastening each of the plurality of securing elements until a shoulder of each of the plurality of securing elements comes into contact with a surface of a fastening member.

10. The method according to claim 1 , further comprising:

synchronously fastening each of the plurality of securing elements within the integrated circuit assembly while the integrated circuit assembly is in a compressed state due to the applied mechanical compression load.

11. The method according to claim 1 , wherein

the mechanical compression load is maintained against the integrated circuit assembly until each of the plurality of securing elements is fastened to the integrated circuit assembly.

12. The method according to claim 1 , further comprising:

fabricating the plurality of orifices in each of the plurality of layer components of the integrated circuit assembly, wherein the fabricating the plurality of orifices includes positioning each of the plurality of orifices along each layer component of the integrated circuit layer according to a first predetermined pitch along a first direction and a second predetermined pitch along a second direction;

aligning each of the plurality of layer components of the integrated circuit assembly according to the plurality of orifices in each of the plurality of layer components.

13. The method according to claim 1 , wherein

each orifice comprises a through hole that extends through each of the plurality of layer components of the integrated layer assembly.

14. The method according to claim 1 , wherein

each orifice comprises a through hole that extends through at least one of the plurality of layer components of the integrated layer assembly and terminates at a cavity within a terminal layer of the integrated circuit assembly.

Assignments (2)
SECURITY INTEREST Recorded Jun 18, 2026
From: CEREBRAS SYSTEMS INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 075845/0844 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2018
From: FRICKER, JEAN-PHILIPPE; JUN, FRANK; KENNEDY, PAUL
To: CEREBRAS SYSTEMS INC.
Reel/Frame 047285/0245 →
Continuity (2)
Provisional Application 62549677 · Aug 24, 2014
Related Publication 20190067052A1 · Feb 28, 2019
Cited By (1)
US 12,463,139