Forming nitrogen-containing low-K gate spacer
A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.
1. A method comprising:
forming a dummy gate stack over a semiconductor region of a wafer; and
depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack, wherein the depositing the gate spacer layer comprises performing an ALD cycle to form a dielectric atomic layer, wherein the ALD cycle comprises:
introducing silylated methyl to the wafer;
purging the silylated methyl;
introducing ammonia to the wafer; and
purging the ammonia.
2. The method of claim 1 further comprising performing an anneal on the wafer after the gate spacer layer is formed, wherein the anneal is performed with the wafer placed in an oxygen-containing gas.
3. The method of claim 2 , wherein the anneal is performed at a temperature in a range between about 400° C. and about 500° C.
4. The method of claim 2 , wherein before the anneal, the gate spacer layer has a first nitrogen atomic percentage, and after the anneal, a portion of the gate spacer layer has a second nitrogen atomic percentage lower than the first nitrogen atomic percentage.
5. The method of claim 2 , wherein before the anneal, the gate spacer layer has a first k value higher than a k value of silicon oxide, and after the anneal, a portion of the gate spacer layer has a second k value lower than the k value of silicon oxide.
6. The method of claim 1 , wherein the depositing the gate spacer layer further comprises introducing ammonia to the wafer before performing the ALD cycle.
7. The method of claim 1 further comprising:
performing an anisotropic etching on the gate spacer layer to form gate spacers on opposite sides of the dummy gate stack; and
removing the dummy gate stack using dry etch.
8. The method of claim 1 further comprising depositing a high-k dielectric layer as a sealing layer, wherein the high-k dielectric layer comprises a portion separating the dummy gate stack from the gate spacer layer.
9. The method of claim 1 further comprising repeating the ALD cycle until the gate spacer layer has a thickness greater than about 20 Å.
10. A method comprising:
forming a dummy gate stack over a semiconductor region of a wafer;
forming a dielectric layer comprising silicon, nitrogen, oxygen, carbon, and hydrogen, wherein the dielectric layer has a first k value, and the forming the dielectric layer comprises an Atomic Layer Deposition (ALD) cycle comprising:
introducing silylated methyl to the wafer;
purging the silylated methyl;
introducing ammonia to the wafer; and
purging the ammonia; and
performing an anneal on the dielectric layer, wherein after the anneal, the dielectric layer has a second k value lower than the first k value.
11. The method of claim 10 , wherein the anneal is performed at a temperature in a range between about 400° C. and about 500° C.
12. The method of claim 10 , wherein the ALD comprises pulsing silylated methyl and ammonia alternatingly.
13. The method of claim 10 , wherein the anneal is performed in an oxygen-containing environment comprising H 2 O, O 2 , or oxygen radicals.
14. The method of claim 10 , wherein the anneal results in a k value of the dielectric layer to be reduced from a high-k value higher than 4.0 to a low-k value lower than 3.9.
15. The method of claim 10 , wherein the anneal results in a nitrogen atomic percentage in the dielectric layer to be reduced from a first value to a second value, wherein the first value is in a range between about 3 percent and about 30 percent, and the second value is in a range between about 1 percent and about 10 percent.
16. A method comprising:
depositing a dielectric layer on a wafer, wherein the depositing comprises conducting ammonia, silylated methyl, and ammonia sequentially to the wafer;
performing an anneal process on the wafer after the dielectric layer is formed, wherein the anneal process is performed using an oxygen-containing gas; and
patterning the dielectric layer by removing a portion of the dielectric layer.
17. The method of claim 16 further comprising performing a plurality of additional cycles, each comprising:
introducing silylated methyl to the wafer;
purging the silylated methyl;
introducing ammonia to the wafer; and
purging the ammonia.
18. The method of claim 16 , wherein the anneal process is performed at a temperature in a range between about 400° C. and about 500° C.
19. The method of claim 16 , wherein before the anneal process, the dielectric layer has a first nitrogen atomic percentage, and after the anneal process, a portion of the dielectric layer has a second nitrogen atomic percentage lower than the first nitrogen atomic percentage.
20. The method of claim 16 , wherein before the anneal process, the dielectric layer has a first k value higher than a k value of silicon oxide, and after the anneal process, a portion of the dielectric layer has a second k value lower than the k value of silicon oxide.