Short-circuit performance for silicon carbide semiconductor device
A semiconductor device includes a source region configured to provide at least a portion of a MOSFET source of a MOSFET and at least a portion of a JFET source of a JFET. The semiconductor device includes a JFET channel region in series with the source region and a MOSFET channel region of the MOSFET, and disposed between a first JFET gate and a second JFET gate. The semiconductor device includes a JFET drain disposed at least partially between a gate insulator of a gate of the MOSFET and at least a portion of the JFET channel region, and in electrical contact with the first JFET gate and the second JFET gate. Various example implementations of this type of semiconductor device provide a SiC power MOSFET with improved short-circuit capability and durability, with minimal impact on R DS-ON .
1. A semiconductor device, comprising:
a source region configured to provide at least a portion of a MOSFET source of a MOSFET and at least a portion of a JFET source of a JFET;
a JFET channel region in series with the source region and a MOSFET channel region of the MOSFET, and disposed between a first JFET gate and a second JFET gate; and
a JFET drain disposed at least partially between a gate insulator of a gate of the MOSFET and at least a portion of the JFET channel region, and in electrical contact with the first JFET gate and the second JFET gate.
2. The semiconductor device of claim 1 , wherein the JFET channel region provides pinch-off of short-circuit current of the MOSFET during a short-circuit event of the MOSFET.
3. The semiconductor device of claim 2 , wherein, in the JFET channel, a doping concentration, a width W JFET and a length L are configured to cause the pinch-off to occur at a specified short-circuit current.
4. The semiconductor device of claim 3 , wherein a JFET channel dose N D ·W JFET for a value of L is configured to cause the pinch-off to occur at a specified short-circuit current.
5. The semiconductor device of claim 1 , wherein the first JFET gate and the second JFET gate are electrically connected to the source region.
6. The semiconductor device of claim 1 , wherein the first JFET gate is disposed between a surface of the semiconductor device and at least a portion of the JFET channel region.
7. The semiconductor device of claim 1 , wherein the JFET drain is disposed at least partially at a surface of the semiconductor device, and between the first JFET gate and the MOSFET channel region.
8. The semiconductor device of claim 1 , wherein the MOSFET is a vertical power Silicon Carbide (SiC) MOSFET.
9. The semiconductor device of claim 1 , wherein a source contact of the source region is in electrical contact with the source region, the first JFET gate, and the second JFET gate.
10. A semiconductor device, comprising:
a MOSFET; and
a JFET in series with a MOSFET channel region of the MOSFET, the JFET having a first JFET gate and a second JFET gate, both the first JFET gate and the second JFET gate being shorted to a JFET source of the JFET, wherein the first JFET gate is disposed between a surface of the semiconductor device and a JFET channel region of the JFET, and a JFET drain of the JFET is disposed between the first JFET gate and the MOSFET channel region.
11. The semiconductor device of claim 10 , wherein the JFET channel region provides pinch-off of short-circuit current of the MOSFET during a short-circuit event of the MOSFET.
12. The semiconductor device of claim 11 , wherein, in the JFET channel region, a doping concentration, a width W JFET and a length L are configured to cause the pinch-off to occur at a specified short-circuit current.
13. The semiconductor device of claim 12 , wherein a ratio of (N D ·W JFET )/L is configured to cause the pinch-off to occur at a specified short-circuit current.
14. The semiconductor device of claim 10 , wherein a drain current of the JFET, ID JFET , reaches a saturation current ID SAT at a saturation drain voltage of the JFET, VD SAT .
15. The semiconductor device of claim 10 , comprising a source region configured to provide at least a portion of a MOSFET source of the MOSFET and at least a portion of the JFET source of the JFET.
16. The semiconductor device of claim 10 , wherein the JFET drain is disposed at least partially at the surface of the semiconductor device.