Enhancement mode III-nitride devices having an Al
A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al 1-x Si x O layer with 0.2<x<0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.
1. A transistor comprising:
a III-N channel layer;
a III-N barrier layer on the III-N channel layer;
a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer;
an insulator layer on the III-N barrier layer;
a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al 1-x Si x O layer with 0.2<x<0.8, wherein the amorphous Al 1-x Si x O layer includes a nanocrystalline Al 1-x Si x O portion on a side adjacent the III-N channel layer; and
a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.
2. The transistor of claim 1 , wherein a thickness of the amorphous Al 1-x Si x O layer is between about 1 nm and 100 nm.
3. The transistor of claim 1 , wherein the gate electrode comprises a semiconductor material.
4. The transistor of claim 1 , wherein the gate electrode comprises titanium nitride (TiN), indium nitride (InN), p-type poly silicon, tungsten nitride (WN), or indium tin oxide (ITO).
5. The transistor of claim 4 , wherein a composition of the gate electrode is selected such that at room temperature, a threshold voltage of the transistor is greater than 2 V and a threshold voltage hysteresis is less than 0.5 V.
6. The transistor of claim 5 , wherein the transistor is configured such that in operation, an off state blocking voltage of the transistor is greater than 600V.
7. The transistor of claim 1 , wherein a recess in a first portion of the transistor extends through the insulator layer and the III-N barrier layer.
8. The transistor of claim 7 , wherein the gate insulator is at least partially in the recess and contacts the III-N channel layer in the recess.
9. The transistor of claim 8 , wherein the gate electrode is at least partially in the recess.
10. The transistor of claim 1 , wherein a thickness of the nanocrystalline Al 1-x Si x O portion is less than 40% of a thickness of the amorphous Al 1-x Si x O layer.
11. The transistor of claim 1 , wherein the amorphous Al 1-x Si x O layer includes nitrogen.
12. A method of fabricating a III-N device, comprising:
providing a material structure comprising
a III-N barrier layer on a III-N channel layer, and
an insulator layer on the III-N barrier layer;
forming a recess in a first portion of the device, the forming of the recess comprising removing the insulator layer and the III-N barrier layer in the first portion of the device to expose the III-N channel layer in the first portion of the device;
forming an amorphous Al 1-x Si x O layer at least partially in the recess, wherein the amorphous Al 1-x Si x O layer is formed over the channel layer in the first portion of the device; and
forming a gate electrode on the amorphous Al 1-x Si x O layer at least partially in the recess, wherein the gate electrode comprises a compound semiconductor material and a metal;
wherein forming the amorphous Al 1-x Si x O layer includes forming a nanocrystalline Al 1-x Si x O portion on a side adjacent the III-N channel layer.
13. The method of claim 12 , wherein the forming of the amorphous Al 1-x Si x O layer is performed using a metal organic chemical vapor deposition (MOCVD) growth reactor.
14. The method of claim 12 , further comprising annealing the III-N device at an elevated temperature.
15. The method of claim 14 , wherein the forming of the amorphous Al 1-x Si x O layer and the annealing of the III-N device is performed sequentially without exposure to air in a MOCVD growth reactor.
16. The method of claim 14 , wherein the annealing of the III-N device is performed at a temperature greater than 800° C.
17. The method of claim 12 , wherein the gate electrode includes titanium nitride (TiN), indium nitride (InN), p-type poly silicon, tungsten nitride (WN), or indium tin oxide (ITO).
18. The method of claim 12 , further comprising annealing the III-N device in forming gas after the forming of the gate electrode.
19. The method of claim 18 , wherein the annealing is performed at a temperature greater than 350° C.
20. The method of claim 12 , wherein the forming of the amorphous Al 1-x Si x O layer is performed at a deposition temperature greater than 500° C.
21. The method of claim 12 , wherein a thickness of the nanocrystalline Al 1-x Si x O portion is less than 40% of a thickness of the amorphous Al 1-x Si x O layer.
22. The method of claim 12 , wherein forming the amorphous Al 1-x Si x O layer includes incorporating nitrogen into the amorphous Al 1-x Si x O layer to form an Al 1-x Si x ON layer.