Silicon carbide semiconductor device

1. A silicon carbide semiconductor device comprising:

a silicon carbide substrate;

a first silicon carbide layer disposed on the silicon carbide substrate and having a first conductivity type;

a second silicon carbide layer disposed on the first silicon carbide layer and having the first conductivity type;

a third silicon carbide layer disposed on the second silicon carbide layer and having a second conductivity type different from the first conductivity type;

a fourth silicon carbide layer disposed on the third silicon carbide layer and having the first conductivity type; and

a first impurity region formed to extend through the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer, and having the second conductivity type,

a trench being formed in the silicon carbide semiconductor device so as to extend through the fourth silicon carbide layer and the third silicon carbide layer to reach the second silicon carbide layer,

the silicon carbide semiconductor device comprising:

a gate insulating film in contact with a wall of the trench;

a gate electrode in contact with the gate insulating film and filling the trench;

a second impurity region disposed below the trench while being spaced from a bottom of the trench, and having the second conductivity type;

a third impurity region formed below the first impurity region so as to be in contact with the first impurity region, having the second conductivity type, and electrically connected to the second impurity region; and

a fourth impurity region formed between the second impurity region and the third impurity region and having the first conductivity type,

wherein

a depth of the fourth impurity region from an interface between the first silicon carbide layer and the second silicon carbide layer is smaller than a depth of the second impurity region from the interface.

2. The silicon carbide semiconductor device according to claim 1 , wherein

an impurity concentration of the second silicon carbide layer is higher than an impurity concentration of the first silicon carbide layer,

an impurity concentration of the fourth impurity region is higher than the impurity concentration of the second silicon carbide layer, and

an impurity concentration of the second impurity region is higher than the impurity concentration of the fourth impurity region.

3. The silicon carbide semiconductor device according to claim 1 , wherein

when a distance from the bottom of the trench to the second impurity region is expressed as D 1 , a relation of

0.1 μm≤ D 1 ≤3.0 μm

holds.

4. The silicon carbide semiconductor device according to claim 1 , wherein

a width in a lateral direction of the third impurity region is smaller than a width in the lateral direction of the second impurity region.

5. The silicon carbide semiconductor device according to claim 1 , wherein

the width in the lateral direction of the second impurity region is greater than a width in the lateral direction of the trench.

6. The silicon carbide semiconductor device according to claim 1 , wherein

a thickness of the gate insulating film at the bottom of the trench is greater than a thickness of a portion of the gate insulating film which is in contact with a sidewall of the trench.

7. The silicon carbide semiconductor device according to claim 1 , wherein

the sidewall of the trench has a crystal plane orientation of <1-100> or <11-20>.

8. The silicon carbide semiconductor device according to claim 1 , wherein

the trench has a sidewall surface inclined relative to a {000-1} plane.

9. The silicon carbide semiconductor device according to claim 1 , wherein

the silicon carbide semiconductor device is a MOSFET, and

the silicon carbide substrate has the first conductivity type.

10. The silicon carbide semiconductor device according to claim 1 , wherein

the silicon carbide semiconductor device is an IGBT, and

the silicon carbide substrate has the second conductivity type.

11. A silicon carbide semiconductor device comprising:

a silicon carbide substrate;

a first silicon carbide layer disposed on the silicon carbide substrate and having a first conductivity type;

a second silicon carbide layer disposed on the first silicon carbide layer and having the first conductivity type;

a third silicon carbide layer disposed on the second silicon carbide layer and having a second conductivity type different from the first conductivity type;

a fourth silicon carbide layer disposed on the third silicon carbide layer and having the first conductivity type; and

a first impurity region formed to extend through the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer, and having the second conductivity type,

a trench being formed in the silicon carbide semiconductor device so as to extend through the fourth silicon carbide layer and the third silicon carbide layer to reach the second silicon carbide layer,

the silicon carbide semiconductor device comprising:

a gate insulating film in contact with a wall of the trench;

a gate electrode in contact with the gate insulating film and filling the trench;

a second impurity region disposed below the trench while being spaced from a bottom of the trench, and having the second conductivity type;

a third impurity region formed below the first impurity region so as to be in contact with the first impurity region, having the second conductivity type, and electrically connected to the second impurity region; and

a fourth impurity region formed between the second impurity region and the third impurity region and having the first conductivity type,

wherein

an impurity concentration of the second silicon carbide layer is higher than an impurity concentration of the first silicon carbide layer,

an impurity concentration of the fourth impurity region is higher than the impurity concentration of the second silicon carbide layer,

an impurity concentration of the second impurity region is higher than the impurity concentration of the fourth impurity region,

a depth of the fourth impurity region from an interface between the first silicon carbide layer and the second silicon carbide layer is smaller than a depth of the second impurity region from the interface, and

when a distance from the bottom of the trench to the second impurity region is expressed as D 1 , a relation of

0.1 μm≤ D 1 ≤3.0 μm

holds.

12. The silicon carbide semiconductor device according to claim 11 , wherein

a thickness of the gate insulating film at the bottom of the trench is greater than a thickness of a portion of the gate insulating film which is in contact with a sidewall of the trench.

13. The silicon carbide semiconductor device according to claim 11 , wherein

the sidewall of the trench has a crystal plane orientation of <1-100> or <11-20>.

14. The silicon carbide semiconductor device according to claim 11 , wherein

the trench has a sidewall surface inclined relative to a {000-1} plane.

15. A silicon carbide semiconductor device comprising:

a silicon carbide substrate;

a first silicon carbide layer disposed on the silicon carbide substrate and having a first conductivity type;

a second silicon carbide layer disposed on the first silicon carbide layer and having the first conductivity type;

a third silicon carbide layer disposed on the second silicon carbide layer and having a second conductivity type different from the first conductivity type;

a fourth silicon carbide layer disposed on the third silicon carbide layer and having the first conductivity type; and

a first impurity region formed to extend through the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer, and having the second conductivity type,

a trench being formed in the silicon carbide semiconductor device so as to extend through the fourth silicon carbide layer and the third silicon carbide layer to reach the second silicon carbide layer,

the silicon carbide semiconductor device comprising:

a gate insulating film in contact with a wall of the trench;

a gate electrode in contact with the gate insulating film and filling the trench;

a second impurity region disposed below the trench while being spaced from a bottom of the trench, and having the second conductivity type;

a third impurity region formed below the first impurity region so as to be in contact with the first impurity region, having the second conductivity type, and electrically connected to the second impurity region; and

a fourth impurity region formed between the second impurity region and the third impurity region and having the first conductivity type,

wherein

an impurity concentration of the second silicon carbide layer is higher than an impurity concentration of the first silicon carbide layer,

an impurity concentration of the fourth impurity region is higher than the impurity concentration of the second silicon carbide layer,

an impurity concentration of the second impurity region is higher than the impurity concentration of the fourth impurity region,

a depth of the fourth impurity region from an interface between the first silicon carbide layer and the second silicon carbide layer is smaller than a depth of the second impurity region from the interface,

when a distance from the bottom of the trench to the second impurity region is expressed as D 1 , a relation of

0.1 μm≤ D 1 ≤3.0 μm

holds,

a width in a lateral direction of the third impurity region is smaller than a width in the lateral direction of the second impurity region, and

the width in the lateral direction of the second impurity region is greater than a width in the lateral direction of the trench.

16. The silicon carbide semiconductor device according to claim 15 , wherein

a thickness of the gate insulating film at the bottom of the trench is greater than a thickness of a portion of the gate insulating film which is in contact with a sidewall of the trench.

17. The silicon carbide semiconductor device according to claim 15 , wherein

the sidewall of the trench has a crystal plane orientation of <1-100> or <11-20>.

18. The silicon carbide semiconductor device according to claim 15 , wherein

the trench has a sidewall surface inclined relative to a {000-1} plane.