Array substrate, manufacturing method thereof, display panel
An array substrate, a manufacturing method thereof, and a display panel are provided. The array substrate comprises a base substrate, a plurality of gate lines and gate electrodes on the base substrate, each gate electrode being corresponding to and separate from a respective gate line, a gate insulating layer over the gate electrode and the gate line, the gate insulating layer having a first via hole and a second via hole, the first via hole exposing the gate electrode, the second via hole exposing the gate line, a conductive connection layer and a polysilicon semiconductor layer on the gate insulating layer, the conductive connection layer filling the first via hole and the second via hole to connect the gate line with the gate electrode.
1. An array substrate comprising: a base substrate, a plurality of gate lines and gate electrodes on the base substrate, each gate electrode corresponding to and separate from a respective gate line, a gate insulating layer over the gate electrodes and the gate lines, the gate insulating layer comprising a first via hole and a second via hole, the first via hole exposing a first gate electrode of the plurality of gate electrodes, the second via hole exposing a first gate line of the plurality of gate lines, and a conductive connection layer on the gate insulating layer, the conductive connection layer filling the first via hole and the second via hole to connect the first gate line with the first gate electrode, wherein the gate electrodes and the gate lines are disposed in a same layer, wherein the array substrate further comprises an active layer on the gate insulating layer, the active layer comprises a p-type polysilicon semiconductor layer, a first amorphous silicon semiconductor layer and an n-type polysilicon semiconductor layer stacked on the gate insulating layer in sequence, and wherein the active layer further comprises a second amorphous silicon semiconductor layer between the gate insulating layer and the first amorphous silicon semiconductor layer.
2. The array substrate according to claim 1 , wherein the array substrate further comprises a source/drain on the n-type polysilicon semiconductor layer.
3. The array substrate according to claim 2 , wherein the conductive connection layer and the source/drain are disposed in a same layer.
4. The array substrate according to claim 1 , wherein an orthographic projection of the p-type polysilicon semiconductor layer on the base substrate at least partially overlaps an orthographic projection of the first gate electrode on the base substrate.
5. A display panel comprising the array substrate according to claim 1 .
6. A manufacturing method for the array substrate according to claim 1 , comprising: forming the plurality of gate lines and gate electrodes on the base substrate, each gate electrode corresponding to and separate from the respective gate line, forming the gate insulating layer over the gate electrodes and the gate lines, the gate insulating layer comprising the first via hole that exposes the first gate electrode of the plurality of gate electrodes and the second via hole that exposes the first gate line of the plurality of gate lines, and forming the p-type polysilicon semiconductor layer on the gate insulating layer.
7. The method according to claim 6 , further comprising: forming a source/drain on the n-type polysilicon semiconductor layer, forming the conductive connection layer on the gate insulating layer, the conductive connection layer filling the first via hole and the second via hole to connect the first gate line with the first gate electrode.
8. The method according to claim 6 , wherein forming the gate insulating layer comprises:
forming, by a patterning process, the gate insulating layer comprising the first via hole and the second via hole.
9. The manufacturing method according to claim 6 , wherein forming the gate insulating layer comprises:
forming an insulating film covering the gate electrodes and the gate lines, and
etching the insulating film to obtain the first via hole that exposes the first gate electrode and the second via hole that exposes the first gate line.
10. The manufacturing method according to claim 6 , wherein forming the p-type polysilicon semiconductor layer on the gate insulating layer comprises:
forming, by a patterning process, the second amorphous silicon semiconductor layer on the gate insulating layer, and performing a local laser annealing process on a region in the second amorphous silicon semiconductor layer corresponding to the first gate electrode to form the p-type polysilicon semiconductor layer.
11. The manufacturing method according to claim 10 , wherein the local laser annealing process is a microlens array (MLA) local laser annealing process.
12. The manufacturing method according to claim 7 , wherein the conductive connection layer is formed on the gate insulating layer by a same patterning process used to form the source/drain.
13. The manufacturing method according to claim 6 , the method further comprising: forming the first amorphous silicon semiconductor layer and the n-type polysilicon semiconductor layer on the p-type polysilicon semiconductor layer.
14. The manufacturing method according to claim 6 , wherein an orthographic projection of the p-type polysilicon semiconductor layer on the base substrate at least partially overlaps that of the first gate electrode on the base substrate.