IP Library Granted Patent US 10,777,722
Granted Patent B2
US 10,777,722 · App. 16/105,755 · Granted Sep 15, 2020

Methods and apparatus providing thermal isolation of photonic devices

Inventors: Roy Meade (Oakland, CA); Gurtej Sandhu (Boise, ID)
Assignee: Micron Technology, Inc.
H01L33/64G02B6/12G02B6/12004G02B6/12007G02F1/0147G02F1/3132G02F1/3133G02B2006/121G02B2006/12135G02F2203/15H01L2933/0075
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,777,722
App. No.
16/105,755
Granted
Sep 15, 2020
Kind
B2
Abstract

Described embodiments include photonic integrated circuits and systems with photonic devices, including thermal isolation regions for the photonic devices. Methods of fabricating such circuits and systems are also described.

Claims (26)

1. An integrated structure comprising:

a substrate having an upper surface;

a trench formed in the upper surface of the substrate;

a device formation region over the upper surface of the substrate;

a temperature-sensitive photonic device formed in the device formation region;

a heating device formed in the device formation region for heating the temperature-sensitive photonic device, wherein the heating device is located over the trench; and

a thermal isolation region formed directly under the heating device and laterally separated from the temperature-sensitive photonic device such that the thermal isolation region is not formed directly under the temperature-sensing photonic device, wherein the thermal isolation region is located in the trench, such that the thermal isolation region is provided in the upper surface of the substrate, and wherein the thermal isolation region thermally isolates the substrate from the heating device.

2. The integrated structure of claim 1 , wherein the thermal isolation region and the trench both extend under the temperature-sensitive photonic device.

3. The integrated structure of claim 1 , further comprising a waveguide formed in the device formation region, and wherein the thermal isolation region and the trench both extend under the waveguide.

4. The integrated structure of claim 1 , further comprising a waveguide formed in the device formation region, and wherein the waveguide is separated from the trench by a portion of the substrate.

5. The integrated structure of claim 1 , wherein the thermal isolation region comprises a physical gap between the heating device and substrate.

6. The integrated structure of claim 5 , wherein the physical gap is further provided on a side of the heating device.

7. The integrated structure of claim 1 , wherein the thermal isolation region is a first thermal isolation region, and further comprising a second thermal isolation region under the temperature-sensitive photonic device.

8. The integrated structure of claim 7 , wherein the second thermal isolation region is located in the trench.

9. The integrated structure of claim 7 , wherein the first thermal isolation region and the second thermal isolation comprise separate materials.

10. The integrated structure of claim 7 , wherein the trench is a first trench, and wherein the second thermal isolation region is located in a second trench.

11. The integrated structure of claim 1 , wherein the thermal isolation region comprises a low thermal conductivity material within the trench.

12. The integrated structure of claim 11 , wherein the low thermal conductivity material has a thermal conductivity that is less than approximately 0.006 W/cm° C.

13. The integrated structure of claim 11 , wherein the low thermal conductivity material comprises an oxide doped with a material having a lower thermal conductivity than the oxide.

14. The integrated structure of claim 11 , wherein the low thermal conductivity material comprises silicon dioxide that has been doped with a dopant having a lower dielectric constant than the silicon dioxide.

15. The integrated structure of claim 14 , wherein the dopant comprises fluorine or carbon.

16. The integrated structure of claim 11 , wherein the low thermal conductivity material comprises porous silicon dioxide.

17. The integrated structure of claim 11 , wherein the low thermal conductivity material comprises spin-on silicon dioxide.

18. The integrated structure of claim 1 , wherein the temperature-sensitive photonic device comprises a carrier wave modulator.

19. The integrated structure of claim 1 , wherein the temperature-sensitive photonic device comprises a laser.

20. The integrated structure of claim 1 , wherein the trench and the thermal isolation region form a shallow trench isolation region.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2018
From: MEADE, ROY; SANDHU, GURTEJ
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046678/0506 →
Continuity (3)
Continuation 15056845 · Feb 29, 2016
Division 13524446 · Jun 15, 2012
Related Publication 20190013452A1 · Jan 10, 2019