FAN-OUT SEMICONDUCTOR PACKAGE

1 . A fan-out semiconductor package comprising:

a first semiconductor chip;

a redistribution portion disposed below the semiconductor chip;

a reinforcing member disposed on the redistribution portion and surrounding the semiconductor chip; and

an encapsulant disposed on the redistribution portion to embed the semiconductor chip and the reinforcing member therein.

2 . The fan-out semiconductor package of claim 1 , wherein the reinforcing member includes sections each having a bar shape and spaced apart from each other, and

the sections of the reinforcing member are disposed at edges of the redistribution portion, respectively.

3 . The fan-out semiconductor package of claim 1 , wherein the reinforcing member includes at least one selected from the group consisting of silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), copper (Cu), and platinum (Pt), or mixtures thereof.

4 . The fan-out semiconductor package of claim 1 , wherein the redistribution portion includes an insulating layer and at least one conductor layer disposed in the insulating layer.

5 . The fan-out semiconductor package of claim 4 , wherein the redistribution portion further includes an underfill disposed on an upper surface of the insulating layer and a passivation layer disposed on a lower surface of the insulating layer.

6 . The fan-out semiconductor package of claim 5 , wherein the underfill is disposed inwardly of the reinforcing member, and the encapsulant is disposed outwardly of the reinforcing member.

7 . The fan-out semiconductor package of claim 6 , wherein, the underfill is in contact with the insulating layer of the redistribution portion disposed inwardly of the reinforcing member, and

the encapsulant is in contact with a portion of the insulating layer of the redistribution portion disposed outwardly of the reinforcing member.

8 . The fan-out semiconductor package of claim 5 , wherein the conductor layer includes a wiring portion having at least one layer and a lower surface electrode exposed to a lower surface of the passivation layer.

9 . The fan-out semiconductor package of claim 8 , further comprising an electrical connection structure connected to the lower surface electrode.

10 . The fan-out semiconductor package of claim 4 , wherein the reinforcing member is connected to the conductor layer.

11 . The fan-out semiconductor package of claim 1 , wherein the reinforcing member is not electrically connected to the redistribution portion.

12 . The fan-out semiconductor package of claim 1 , further comprising:

a connection via having one end connected to the reinforcing member and the other end exposed to an upper surface of the encapsulant; and

a heat dissipation member connected to the connection via and covering the upper surface of the encapsulant.

13 . The fan-out semiconductor package of claim 12 , wherein a lower surface of the heat dissipation member is in contact with an upper surface of the semiconductor chip.

14 . The fan-out semiconductor package of claim 12 , wherein the connection via and the heat dissipation member are made of the same material as that of the reinforcing member.

15 . The fan-out semiconductor package of claim 12 , wherein the connection via has a bar shape corresponding to that of the reinforcing member.

16 . The fan-out semiconductor package of claim 1 , further comprising:

a plurality of connection vias each having one end connected to the reinforcing member and the other end exposed to an upper surface of the encapsulant, disposed on the reinforcing member to be spaced apart from each other, and each having a pillar shape; and

a heat dissipation member connected to the plurality of connection vias and covering the upper surface of the encapsulant.

17 . The fan-out semiconductor package of claim 1 , further comprising a second semiconductor chip disposed side by side with the first semiconductor chip in a horizontal direction,

wherein the reinforcing member surrounds the second semiconductor chip, and

the encapsulant embeds the second semiconductor chip.

18 . A fan-out semiconductor package comprising:

a redistribution portion;

a first semiconductor chip disposed on an upper surface of the redistribution portion;

a reinforcing member disposed at an edge of the redistribution portion;

an encapsulant disposed on the redistribution portion, an upper surface of the first semiconductor chip being exposed from the encapsulant and the reinforcing member being embedded in the encapsulant;

a connection via connected to the reinforcing member and having one end exposed to an upper surface of the encapsulant; and

a heat dissipation member connected to the connection via and covering the encapsulant to be in contact with the upper surface of the first semiconductor chip.

19 . The fan-out semiconductor package of claim 18 , further comprising a second semiconductor chip disposed side by side with the first semiconductor chip on the upper surface of the redistribution portion,

wherein an upper surface of the second semiconductor chip is exposed from the encapsulant, and

the heat dissipation member is in contact with the upper surface of the second semiconductor chip.