Packaged microelectronic devices having stacked interconnect elements and methods for manufacturing the same
Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.
1. A method of forming a plurality of microelectronic devices on a semiconductor workpiece, the method comprising:
placing a plurality of first interconnect elements on a side of a semiconductor workpiece;
forming a protective layer on the side of the workpiece such that the protective layer has a top surface and a top portion of the first interconnect structures protrudes from the top surface of the protective layer by a distance;
reshaping the first interconnect elements by heating the first interconnect elements; and
coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed, wherein the second portion is opposite the first portion.
2. The method of claim 1 wherein:
the individual first interconnect elements comprise a conductive member having a proximal end at the side of the workpiece and a distal end opposite the proximal end; and
reshaping the first interconnect elements comprises forming a generally flat surface at the distal end of the individual first interconnect elements.
3. The method of claim 1 wherein reshaping the first interconnect elements comprises reconfiguring the first interconnect elements without removing material from the first interconnect elements.
4. The method of claim 1 further comprising constructing a redistribution structure on the side of the semiconductor workpiece.
5. The method of claim 4 , further comprising depositing a protective layer onto the redistribution structure with the first interconnect elements protruding from a top surface of the protective layer by a distance.
6. The method of claim 1 wherein the side of the semiconductor workpiece is a first side, and wherein the method further comprises providing an alignment feature on a second side of the workpiece opposite the first side.
7. The method of claim 6 further comprising aligning the second interconnect elements with corresponding first interconnect elements using the alignment feature on the second side of the workpiece.
8. The method of claim 7 wherein the alignment feature comprises a first alignment feature, and wherein the method further comprises:
marking the protective layer with a second alignment feature.
9. A method of forming a plurality of microelectronic devices on a semiconductor workpiece, the method comprising:
constructing a redistribution structure on an active side of a semiconductor workpiece;
providing an alignment feature on a backside of the workpiece opposite the active side;
forming a plurality of first interconnect elements on the redistribution structure with the first interconnect elements projecting from the redistribution structure;
reconfiguring the first interconnect elements without removing material from the first interconnect elements; and
aligning and attaching a plurality of free second interconnect elements with corresponding first interconnect elements using the alignment feature on the backside of the workpiece.
10. The method of claim 9 , further comprising depositing a protective layer onto the redistribution structure with the first interconnect elements protruding from a top surface of the protective layer by a distance.
11. The method of claim 9 wherein the alignment feature comprises a first alignment feature, and wherein the method further comprises:
depositing a protective layer onto the redistribution structure; and
marking the protective layer with a second alignment feature.
12. The method of claim 9 wherein the individual first interconnect elements comprise a conductive member having a proximal end at the active side of the workpiece and a distal end opposite the proximal end.
13. The method of claim 12 further comprising forming a generally flat surface at the distal end of the individual first interconnect elements.
14. The method of claim 12 further comprising reconfiguring the first interconnect elements without removing material from the first interconnect elements.
15. The method of claim 9 wherein reconfiguring the first interconnect elements includes reshaping the first interconnect elements by heating the first interconnect elements.