Semiconductor memory device and method of fabricating the same
Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.
1. A semiconductor memory device comprising:
a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate;
a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate;
a storage node contact electrically connected to the second impurity doped region;
a first spacer and a second spacer disposed between the bit line and the storage node contact; and
an air gap region disposed between the first spacer and the second spacer,
wherein the first spacer covers a sidewall of the bit line, and the second spacer is adjacent to the storage node contact,
the first spacer further covers sidewalls and a bottom surface of a lower buried dielectric pattern formed under the air gap region, and
a top end of the first spacer has a height higher than a height of a top end of the second spacer.
2. The semiconductor memory device of claim 1 , wherein a top surface of the storage node contact has a height lower than the height of the top end of the second spacer.
3. The semiconductor memory device of claim 1 , further comprising:
a landing pad electrically connected to the storage node contact;
a bit line capping pattern disposed on the bit line;
a recess region disposed in the bit line capping pattern, the recess region whose sidewall at least a part is shared by the landing pad and whose floor surface is adjacent to the air gap region; and
an upper buried dielectric pattern disposed in the recess region,
wherein the upper buried dielectric pattern comprises:
a first upper buried dielectric pattern being in contact with the sidewall of the recess region and limiting a top end of the air gap region; and
a second upper buried dielectric pattern filling the recess region,
wherein the first upper buried dielectric pattern has a density less than a density of the second upper buried dielectric pattern.
4. The semiconductor memory device of claim 3 , wherein each of the first and second upper buried dielectric patterns comprises at least one of a silicon nitride layer and a silicon carbonitride layer.
5. The semiconductor memory device of claim 3 , further comprising a third upper buried dielectric pattern narrowing an upper width of the air gap region at the floor surface of the recess region,
wherein the third upper buried dielectric pattern has a density less than the density of the first upper buried dielectric pattern.
6. The semiconductor memory device of claim 5 , wherein each of the first and third upper buried dielectric patterns comprises carbon,
wherein a carbon content of the first upper buried dielectric pattern is less than a carbon content of the third upper buried dielectric pattern.
7. The semiconductor memory device of claim 1 , further comprising a landing pad electrically connected to the storage node contact and vertically overlapping a portion of the bit line,
wherein the bit line comprises:
a first sidewall vertically overlapping the landing pad; and
a second sidewall not vertically overlapping the landing pad, and
wherein the air gap region comprises:
a first air gap region adjacent to the first sidewall; and
a second air gap region adjacent to the second sidewall,
wherein a top end of the first air gap region has a height higher than a height of a top end of the second air gap region.
8. The semiconductor memory device of claim 1 , wherein the storage node contact is provided in plural and the plurality of storage node contacts are spaced apart from each other in a row along the bit line,
the semiconductor memory device further comprises an insulation fence disposed between the plurality of storage node contacts, and
the air gap region extends to be disposed between the insulation fence and the bit line.
9. The semiconductor memory device of claim 8 , further comprising a landing pad electrically connected to a storage node contact of the plurality of storage node contacts and vertically overlapping a portion of the bit line and a portion of the insulation fence,
wherein the air gap region comprises:
a first air gap region not vertically overlapping the landing pad between the bit line and the storage node contact;
a second air gap region vertically overlapping the landing pad between the bit line and the storage node contact; and
a third air gap region vertically overlapping the landing pad between the bit line and the insulation fence,
wherein a top end of the second air gap region is higher than a top end of the first air gap region and lower than a top end of the third air gap region.
10. The semiconductor memory device of claim 1 , wherein a top end of the air gap region is higher than a top surface of the bit line.
11. A semiconductor memory device comprising:
a bit line crossing over a semiconductor substrate;
a bit line capping pattern disposed on the bit line;
a plurality of storage node contacts disposed adjacent to a side of the bit line and arranged in a row along the bit line;
a plurality of insulation fences disposed adjacent to the side of the bit line and between the plurality of storage node contacts;
a plurality of landing pads electrically connected to the plurality of storage node contacts and vertically overlapping a portion of the bit line, and
an air gap region disposed between the bit line and the plurality of storage node contacts and between the bit line and the plurality of insulation fences,
wherein a top end of the air gap region is higher than a top surface of the bit line, and
the air gap region comprises:
a first air gap region not vertically overlapping the plurality of landing pads between the bit line and the plurality of storage node contacts;
a second air gap region vertically overlapping the plurality of landing pads between the bit line and the plurality of storage node contacts; and
a third air gap region vertically overlapping the plurality of landing pads between the bit line and the plurality of insulation fences,
wherein a top end of the second air gap region is higher than a top end of the first air gap region and lower than a top end of the third air gap region.
12. The semiconductor memory device of claim 11 , further comprising a first spacer and a second spacer that are between the bit line and the plurality of storage node contacts and between the bit line and the plurality of insulation fences,
wherein the first spacer and the second spacer are spaced apart from each other to define the air gap region,
the first spacer is adjacent to the bit line, and the second spacer is adjacent to the plurality of storage node contacts and the plurality of insulation fences, and
a top end of the first spacer is higher than a top end of the second spacer.
13. The semiconductor memory device of claim 12 , further comprising a third spacer covering an upper sidewall of the first spacer.
14. The semiconductor memory device of claim 13 , wherein a top surface of each of the plurality of storage node contacts is lower than the top end of the second spacer and exposes an upper sidewall of the second spacer, and
the semiconductor memory device further comprises a fourth spacer covering a sidewall of the third spacer and the upper sidewall of the second spacer.
15. The semiconductor memory device of claim 12 , wherein a top surface of each of the plurality of storage node contacts has a height lower than a height of the top end of the second spacer.
16. The semiconductor memory device of claim 11 , further comprising:
a first doped region disposed in the semiconductor substrate and electrically connected to the bit line;
a second doped region disposed in the semiconductor substrate and electrically connected to each of the plurality of storage node contacts; and
a bit line contact electrically connecting the bit line and the first doped region to each other,
wherein a top surface of the first doped region is lower than a top surface of the second doped region.
17. A semiconductor memory device comprising:
a bit line crossing over a semiconductor substrate;
a bit line capping pattern disposed on the bit line;
a plurality of storage node contacts disposed adjacent to a side of the bit line and arranged in a row along the bit line;
a plurality of insulation fences disposed adjacent to the side of the bit line and between the plurality of storage node contacts;
an air gap region disposed between the bit line and the plurality of storage node contacts and between the bit line and the plurality of insulation fences;
a landing pad electrically connected to each of the plurality of storage node contacts;
a recess region whose sidewall is shared by the landing pad and whose floor surface is adjacent to the air gap region, the recess region vertically overlapping the bit line capping pattern; and
a buried dielectric pattern disposed in the recess region,
wherein a top end of the air gap region is higher than a top surface of the bit line, and
the buried dielectric pattern comprises:
a first buried dielectric pattern in contact with the sidewall of the recess region and limiting the top end of the air gap region;
a second buried dielectric pattern filling the recess region; and
a third buried dielectric pattern narrowing an upper width of the air gap region at the floor surface of the recess region,
wherein the first buried dielectric pattern has a density less than a density of the second buried dielectric pattern, and
the density of the first buried dielectric pattern is greater than a density of the third buried dielectric pattern.
18. The semiconductor memory device of claim 17 , wherein each of the first and second buried dielectric patterns comprises carbon, and
a carbon content of the first buried dielectric pattern is greater than a carbon content of the second buried dielectric pattern.