Methods of manufacturing semiconductor devices
A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.
1. A method of manufacturing a semiconductor device, comprising:
forming a plurality of bit line structures in a cell region of a substrate;
forming a gate structure in core/peripheral regions of the substrate;
forming a lower contact plug and an upper contact plug between the bit line structures, wherein the lower contact plug and the upper contact plug are vertically stacked;
forming a capping insulation layer on a first bit line structure of the plurality of bit line structures, on the upper contact plug in the cell region, and on the gate structure in the core/peripheral regions;
forming a first photoresist pattern for forming landing pad patterns in the cell region and contact plugs in the core/peripheral regions on the capping insulation layer, wherein the first photoresist pattern is formed by performing a first exposure process;
etching layers using the first photoresist pattern as an etch mask to form first openings in the cell region and second openings in the core/peripheral regions;
forming a second photoresist pattern for forming wirings in the core/peripheral regions on the capping insulation layer, wherein the second photoresist pattern is formed by performing a second exposure process;
etching layers using the second photoresist pattern as an etch mask to form third openings in communication with the second openings in the core/peripheral regions; and
filling the first openings, the second openings, and the third openings with a first metal material to form the landing pad patterns in the first openings, the contact plugs in the second openings, and the wirings in the third openings.
2. The method of claim 1 , wherein the first exposure process is performed by an EUV exposure process using light having a wavelength of about 13.5 nm.
3. The method of claim 1 , wherein the second exposure process is performed by an EUV exposure process using light having a wavelength of about 13.5 nm.
4. The method of claim 1 , wherein the etching of the layers using the first photoresist pattern as an etch mask to form the first openings in the cell region and the second openings in the core/peripheral regions comprises:
etching layers in the cell region and the core/peripheral regions exposed by the first photoresist pattern to form the first openings in the cell region and preliminary second openings in the core/peripheral regions; and
additionally etching layers under the preliminary second openings in the core/peripheral regions to form the second openings in the core/peripheral regions,
wherein a lower surface of each of the second openings is lower than a lower surface of each of the first openings.
5. The method of claim 4 , wherein the additionally etching layers under the preliminary second openings in the core/peripheral regions comprises:
forming an additional photoresist pattern exposing only the preliminary second openings in the core/peripheral regions, and
etching the layers using the additional photoresist pattern as an etching mask.
6. The method of claim 5 , wherein the additional photoresist pattern is formed by performing an exposure process having a lower resolution than an EUV exposure process.
7. The method of claim 1 , wherein each of the landing pad pattern and the wirings has a dimension less than 20 nanometers (nm) and a pitch less than 40 nm, and wherein an arrangement density of the contact plugs is lower than an arrangement density of the landing pad patterns and an arrangement density of the wirings.
8. The method of claim 1 , wherein one of the first openings is formed by etching portions of the capping insulation layer, the upper contact plug, and one of the bit line structures, and wherein an upper sidewall of the upper contact plug is exposed by the one of the first openings.
9. The method of claim 1 , wherein one of the bit line structures includes a conductive pattern, a metal pattern, and a capping pattern that are sequentially stacked, and
wherein an upper portion of the capping pattern is exposed by one of the first openings.
10. The method of claim 1 , wherein filling the first openings, the second openings, and the third openings with the first metal material to form the landing pad patterns in the first openings, the contact plugs in the second openings, and the wirings in the third openings comprises:
forming a barrier layer and a metal layer on the capping insulation layer to fill the first openings, the second openings, and the third openings; and
planarizing the metal layer and the barrier layer until the capping insulation layer is exposed.
11. The method of claim 10 , wherein a planarization process for planarizing the metal layer includes a chemical mechanical polishing process.
12. The method of claim 1 , wherein the lower contact plug includes polysilicon doped with impurities, and wherein the upper contact plug includes a second metal material.
13. The method of claim 1 , wherein an uppermost surface of the upper contact plug is coplanar with an uppermost surface of one of the bit line structures.
14. The method of claim 1 , wherein the contact plugs include a first contact plug and a second contact plug, and
wherein the first contact plug contacts the substrate, and
wherein the second contact plug is electrically connected to an end portion of one of the bit line structures.
15. A method of manufacturing a semiconductor device, comprising:
forming a first gate structure in a first recess in a cell region of a substrate;
forming a plurality of bit line structures in the cell region of the substrate;
forming a second gate structure in core/peripheral regions of the substrate;
forming a contact plug structure between two of the plurality of bit line structures;
forming a capping insulation layer on a first bit line structure of the plurality of bit line structures, on the contact plug structure in the cell region, and on the second gate structure in the core/peripheral regions;
forming a first photoresist pattern including first openings in the cell region and second openings in the core/peripheral regions on the capping insulation layer, wherein the first photoresist pattern is formed by performing an EUV exposure process using light having a wavelength of about 13.5 nanometers (nm);
etching layers using the first photoresist pattern as an etch mask to form third openings exposing at least a portion of the contact plug structure in the cell region and fourth openings in the core/peripheral regions; and
forming a second photoresist pattern including fifth openings extending in a direction in the core/peripheral regions on the capping insulation layer, wherein the second photoresist pattern is formed by performing an EUV exposure process using light having a wavelength of about 13.5 nm;
etching layers using the second photoresist pattern as an etch mask to form sixth openings in communication with the fourth openings in the core/peripheral regions; and
filling the third openings, the fourth openings, and the sixth openings with a metal material to form landing pad patterns in the third openings, contact plugs in the fourth openings, and wirings in the sixth openings.
16. The method of claim 15 , wherein etching the layers using the first photoresist pattern as an etch mask to form the third openings in the cell region and the fourth openings in the core/peripheral regions comprises:
etching layers in the cell region and the core/peripheral regions exposed by the first photoresist pattern to form the third openings in the cell region and preliminary fourth openings in the core/peripheral regions; and
additionally etching layers under the preliminary fourth openings in the core/peripheral regions to form the fourth openings in the core/peripheral regions,
wherein a lower surface of each of the fourth openings is lower than a lower surface of each of the third openings.
17. The method of claim 15 , wherein filling the third openings, the fourth openings, and the sixth openings with the metal material to form the landing pad patterns in the third openings, the contact plugs in the fourth openings, and the wirings in the sixth openings comprises:
forming a barrier layer and a metal layer on the capping insulation layer to fill the third openings, the fourth openings, and the sixth openings; and
planarizing the metal layer and the barrier layer until the capping insulation layer is exposed.
18. The method of claim 17 , further comprising:
after planarizing the metal layer and the barrier layer, partially etching the metal layer and the barrier layer in one of the third openings such that an upper surface of each of the contact plugs is lower than an upper entrance portion of the one of the third openings.
19. A method of manufacturing a semiconductor device, comprising:
forming a first gate structure in a first recess in a cell region of a substrate;
forming a plurality of bit line structures in the cell region of the substrate;
forming a second gate structure in core/peripheral regions of the substrate;
forming a contact plug structure between the bit line structures;
forming a capping insulation layer on a first bit line structure of the plurality of bit line structures, on the contact plug structure in the cell region, and on the second gate structure in the core/peripheral regions;
forming a first photoresist pattern including first openings in the cell region and second openings in the core/peripheral regions on the capping insulation layer, wherein the first photoresist pattern is formed by performing an EUV exposure process using light having a wavelength of about 13.5 nm;
etching layers using the first photoresist pattern as an etch mask to form third openings exposing at least a portion of the contact plug structure in the cell region and fourth openings in the core/peripheral regions; and
filling the third openings and the fourth openings with a metal material to form landing pad patterns in the third openings and contact plugs in the fourth openings.
20. The method of claim 19 , further comprising:
forming a wiring on the contact plugs in the core/peripheral regions of the substrate, wherein the wiring is electrically connected to the contact plugs.