Semiconductor device and method for fabricating the same
Semiconductor devices including a capacitor in which electrostatic capacity is improved by a simplified process and/or methods for fabricating the same are provided. The semiconductor device including an insulating structure defining a first trench on a substrate, a first conductive layer in the insulating structure, a first portion of an upper surface of the first conductive layer exposed by the first trench, a capacitor structure including a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, the first electrode pattern extending along sidewalls and a bottom surface of the first trench and an upper surface of the insulating structure, and a first wiring pattern on the capacitor structure may be provided.
1. A semiconductor device comprising:
an insulating structure defining a first trench on a substrate;
a first conductive layer in the insulating structure, a first portion of an upper surface of the first conductive layer exposed by the first trench;
a capacitor structure including a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, the first electrode pattern extending along sidewalls and a bottom surface of the first trench and an upper surface of the insulating structure; and
a first wiring pattern on the capacitor structure,
wherein a first distance from the first trench to a distal end of the first electrode pattern is shorter than a second distance from the first trench to a distal end of the dielectric pattern.
2. The semiconductor device of claim 1 , wherein
the dielectric pattern extends along a profile of an upper surface of the first electrode pattern, and
the second electrode pattern extends along a profile of an upper surface of the dielectric pattern.
3. The semiconductor device of claim 1 , further comprising:
a second wiring pattern extending along the upper surface of the insulating structure, the second wiring pattern spaced apart from the first wiring pattern, the second wiring pattern connected to a second portion of the upper surface of the first conductive layer.
4. The semiconductor device of claim 3 , further comprising:
a barrier layer between the first conductive layer and the second wiring pattern,
wherein the insulating structure further includes a second trench, which is spaced apart from the first trench and exposes the second portion of the upper surface of the first conductive layer, and
the barrier layer extends along sidewalls and a bottom surface of the second trench and the upper surface of the insulating structure.
5. The semiconductor device of claim 1 , further comprising:
a second conductive layer spaced apart from the first conductive layer in the insulating structure; and
a rewiring pattern extending along the upper surface of the insulating structure, the rewiring pattern spaced apart from the first wiring pattern, the rewiring pattern connected to an upper surface of the second conductive layer.
6. The semiconductor device of claim 5 , further comprising:
a barrier layer between the second conductive layer and the rewiring pattern,
wherein the insulating structure further includes a second trench, which exposes at least a second portion of the upper surface of the second conductive layer, and
the barrier layer extends along sidewalls and a bottom surface of the second trench and along the upper surface of the insulating structure.
7. The semiconductor device of claim 1 , wherein the first electrode pattern and the second electrode pattern include titanium nitride (TiN).
8. The semiconductor device of claim 1 , wherein the first wiring pattern includes aluminum (Al).
9. A semiconductor device comprising:
a first conductive layer on a substrate;
an insulating structure on the first conductive layer, the insulating structure including a first trench and a second trench, the first trench exposing a first portion of an upper surface of the first conductive layer, the second trench exposing a second portion of the upper surface of the first conductive layer and spaced apart from the first trench;
a capacitor structure extending along sidewalls and a bottom surface of the first trench;
a first wiring pattern on the capacitor structure and extending along an upper surface of the insulating structure; and
a second wiring pattern spaced apart from the first wiring pattern, filling the second trench, and extending along the upper surface of the insulating structure.
10. The semiconductor device of claim 9 , further comprising:
a barrier layer extending along sidewalls and a bottom surface of the second trench,
wherein the second wiring pattern extends along an upper surface of the barrier layer.
11. The semiconductor device of claim 10 , wherein
the capacitor structure comprises a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, and
the second electrode pattern is thicker than the barrier layer.
12. The semiconductor device of claim 10 , wherein
the capacitor structure comprises a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, and
the barrier layer and the second electrode pattern comprise a same material.
13. The semiconductor device of claim 9 , wherein a voltage applied to the first wiring pattern is different from a voltage applied to the second wiring pattern.
14. The semiconductor device of claim 9 , wherein the first wiring pattern and the second wiring pattern comprise a same material.
15. The semiconductor device of claim 9 , further comprising:
a second conductive layer in the insulating structure and spaced apart from the first conductive layer; and
a rewiring pattern extending along an upper surface of the insulating structure, the rewiring pattern spaced from the first wiring pattern the rewiring pattern connected to an upper surface of the second conductive layer.
16. A semiconductor device comprising:
an insulating structure defining a first trench, on a substrate;
a first conductive layer in the insulating structure, a first portion of an upper surface of the first conductive layer exposed by the first trench;
a first electrode pattern extending along sidewalls and a bottom surface of the first trench;
a dielectric pattern covering an upper surface and sidewalls of the first electrode pattern;
a second electrode pattern extending along an upper surface of the dielectric pattern; and
a first wiring pattern extending along an upper surface of the second electrode pattern.
17. The semiconductor device of claim 16 , wherein the dielectric pattern comprises a first extension extending along the upper surface of the first electrode pattern, and a first protrusion protruding from the first extension and covering the sidewalls of the first electrode pattern.
18. The semiconductor device of claim 17 , wherein the second electrode pattern comprises a second extension extending along the upper surface of the first extension, and a second protrusion protruding from the second extension and extending along an upper surface of the first protrusion.
19. The semiconductor device of claim 17 , wherein the first protrusion is in direct contact with an upper surface of the insulating structure.