DRAM memory cell and method of manufacturing the same

1. A DRAM memory cell comprising:

an interlayer dielectric disposed on a semiconductor substrate;

storage node contact plugs disposed on the semiconductor substrate that are rectangular from a plan view perspective, a long axis of the rectangular storage node contact plugs extending in a direction parallel to a bit line, the storage node contact plugs having sidewalls in contact with the interlayer dielectric, the storage node contact plugs having a first cross-section in the direction parallel to the bit line, the first cross-section substantially Y-shaped in a region where the sidewalls contact the interlayer dielectric; and

storage node electrodes disposed on the interlayer dielectric and in contact with the storage node contact plugs, the storage node electrodes contacting their respective storage node contact plugs at locations that are substantially offset, in the direction parallel to the bit line, from a center of the storage node contact plug.

2. The memory cell of claim 1 , wherein the storage node electrodes are arranged in a plurality of rows and columns, and wherein a storage node electrode in a first column and a nearest storage node electrode in a second column that is adjacent to the first column lie on a line that is not perpendicular to the plurality of columns.

3. The memory cell of claim 1 , the storage node contact plugs having a second cross-section in a direction perpendicular to the bit line, the second cross-section substantially rectangular in a region where the sidewalls are adjacent to the interlayer dielectric.

4. A DRAM memory cell comprising:

a semiconductor substrate where a plurality of active regions are defined;

word line structures that are disposed on the semiconductor substrate to cross over the active regions;

first contact pads and second contact pads, each of which is formed in each of the active regions on both sides of the word line structures;

bit line structures that are electrically connected to the first contact pads, electrically isolated from the word line structures, and disposed perpendicular to the word line structures;

an interlayer dielectric that is formed on the semiconductor substrate where the bit line structures are formed;

storage node contact plugs that are rectangular from a plan view perspective, that penetrate the interlayer dielectric, and that are connected to the second contact pads, a long axis of the rectangular storage node contact plugs extending in a direction parallel to the bit line structures, the storage node contact plugs disposed such that an entrance portion is wider than a contacting portion in a direction parallel to the bit line structures; and

storage node electrodes that are formed on the interlayer dielectric in contact with the storage node contact plugs, wherein from a plan view perspective, the storage node electrodes are disposed to be zigzag on the storage node contact plugs in the same column and diagonally disposed throughout the semiconductor substrate.

5. The memory cell of claim 4 , wherein the storage node contact plugs are formed in gaps between the bit line structures.

6. The memory cell of claim 4 , wherein each of the active regions has a T shape rotated by 90°, the active regions in every second row are disposed to correspond to the gaps between the active regions in adjacent rows, and a pair of word line structures are disposed to cross over one active region.

7. The memory cell of claim 4 , further comprising contact spacers between the storage node contact plugs and the interlayer dielectric and between the storage node contact plugs and the bit line structures.

8. The memory cell of claim 4 , wherein a cross-section of the storage node contact plugs in a direction parallel to the word line structures is substantially rectangular in a region where the storage node contact plugs are adjacent to the interlayer dielectric.

9. A DRAM memory cell comprising:

a semiconductor substrate having active regions;

word line structures that are disposed on the semiconductor substrate to cross over the active regions;

first contact pads and second contact pads, each of which is formed in each of the active regions on both sides of the word line structures;

bit line structures that are electrically connected to the first contact pads, electrically isolated from the word line structures, and disposed perpendicular to the word line structures;

an interlayer dielectric disposed on the semiconductor substrate where the bit line structures are formed;

storage node contact plugs that penetrate the interlayer dielectric and are connected to the second contact pads, the storage node contact plugs disposed in gaps between the bit line structures, and, in a direction parallel to the bit line structures, the storage node contact plugs are disposed such that an entrance portion is wider than a contacting portion; and

storage node electrodes disposed on the interlayer dielectric in contact with the storage node contact plugs, wherein from a plan view perspective, the storage node electrodes are disposed to be zigzag on the storage node contact plugs in the same column and diagonally disposed throughout the semiconductor substrate.

10. The memory cell of claim 9 , wherein each of the active regions has a T shape rotated by 90°, the active regions in every second row are disposed to correspond to the gaps between the active regions in adjacent rows, and a pair of word line structures are disposed to cross over one active region.

11. The memory cell of claim 9 , further comprising contact spacers between the storage node contact plugs and the interlayer dielectric and between the storage node contact plugs and the bit line structures.