Microfabricated ultrasonic transducers and related apparatus and methods
Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.
1. A vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit, comprising:
a complementary metal oxide semiconductor (CMOS) substrate having an integrated circuit therein;
a conductive bottom silicon ultrasonic transducer layer integrated on the CMOS substrate above the integrated circuit;
a silicon membrane having a thickness between 1 micron and 10 microns and integrated with the conductive bottom silicon ultrasonic transducer layer with a plurality of ultrasonic transducer cavities between the bottom silicon ultrasonic transducer layer and the silicon membrane, wherein a first ultrasonic transducer cavity of the plurality of ultrasonic transducer cavities has an in-plane long dimension between 25 microns and 100 microns; and
an electrical contact to the silicon membrane.
2. The vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit of claim 1 , wherein the first ultrasonic transducer cavity of the plurality of ultrasonic transducer cavities is substantially circular.
3. The vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit of claim 1 , wherein the first ultrasonic transducer cavity of the plurality of ultrasonic transducer cavities has a multi-sided contour.
4. The vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit of claim 3 , wherein the first ultrasonic transducer cavity of the plurality of ultrasonic transducer cavities has a square contour.
5. The vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit of claim 1 , wherein the CMOS substrate has a silicon base layer.
6. The vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit of claim 1 , wherein the in-plane long dimension of the first ultrasonic transducer cavity is less than 50 microns.
7. The vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit of claim 1 , wherein the silicon membrane has a thickness less than 5 microns.
8. The vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit of claim 1 , further comprising a silicon oxide layer between the silicon membrane and the conductive bottom silicon ultrasonic transducer layer.
9. The vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit of claim 1 , further comprising a silicon oxide to silicon oxide bond between the silicon membrane and the conductive bottom silicon ultrasonic transducer layer.
10. The vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit of claim 1 , wherein the silicon membrane is conductive and wherein the electrical contact to the silicon membrane does not overlie an ultrasonic transducer cavity of the plurality of ultrasonic transducer cavities.
11. The vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit of claim 1 , wherein the conductive bottom silicon ultrasonic transducer layer is configured to resonate at a first frequency different than a second frequency of resonance of the silicon membrane.
12. The vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit of claim 11 , wherein the second frequency is used for a transmit operation and is configured to be less than the first frequency used for a receive operation.
13. The vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit of claim 11 , wherein a voltage between 20 and 300 Volts is configured to be applied to the silicon membrane during operation of the vertically integrated membrane-based capacitive ultrasonic transducer array and integrated circuit.
14. An integrated capacitive ultrasonic transducer array and integrated circuit, comprising:
an integrated circuit substrate having an integrated circuit therein;
a conductive bottom silicon ultrasonic transducer layer integrated on the integrated circuit substrate above the integrated circuit;
a conductive ultrasonic transducer membrane comprising silicon and having a thickness between 1 micron and 10 microns and bonded with the conductive bottom silicon ultrasonic transducer layer, there being a plurality of ultrasonic transducer cavities between the bottom silicon ultrasonic transducer layer and the conductive ultrasonic transducer membrane, wherein a first ultrasonic transducer cavity of the plurality of ultrasonic transducer cavities has a width between 25 microns and 100 microns; and
an electrical contact to the conductive ultrasonic transducer membrane.
15. The integrated capacitive ultrasonic transducer array and integrated circuit of claim 14 , wherein the first ultrasonic transducer cavity of the plurality of ultrasonic transducer cavities is substantially circular.
16. The integrated capacitive ultrasonic transducer array and integrated circuit of claim 14 , wherein the first ultrasonic transducer cavity of the plurality of ultrasonic transducer cavities has a multi-sided contour.
17. The integrated capacitive ultrasonic transducer array and integrated circuit of claim 16 , wherein the first ultrasonic transducer cavity of the plurality of ultrasonic transducer cavities has a square contour.
18. The integrated capacitive ultrasonic transducer array and integrated circuit of claim 14 , wherein the integrated circuit substrate has a silicon base layer.
19. The integrated capacitive ultrasonic transducer array and integrated circuit of claim 14 , wherein the width of the first ultrasonic transducer cavity is less than 50 microns.
20. The integrated capacitive ultrasonic transducer array and integrated circuit of claim 14 , wherein the conductive ultrasonic transducer membrane has a thickness less than 5 microns.
21. The integrated capacitive ultrasonic transducer array and integrated circuit of claim 14 , further comprising a silicon oxide layer between the conductive ultrasonic transducer membrane and the conductive bottom silicon ultrasonic transducer layer.
22. The integrated capacitive ultrasonic transducer array and integrated circuit of claim 14 , further comprising a silicon oxide to silicon oxide bond between the conductive ultrasonic transducer membrane and the conductive bottom silicon ultrasonic transducer layer.
23. The integrated capacitive ultrasonic transducer array and integrated circuit of claim 14 , wherein the electrical contact to the conductive ultrasonic transducer membrane does not overlie an ultrasonic transducer cavity of the plurality of ultrasonic transducer cavities.
24. The integrated capacitive ultrasonic transducer array and integrated circuit of claim 14 , wherein the conductive bottom silicon ultrasonic transducer layer is configured to resonate at a first frequency different than a second frequency of resonance of the conductive ultrasonic transducer membrane.
25. The integrated capacitive ultrasonic transducer array and integrated circuit of claim 24 , wherein the second frequency is used for a transmit operation and is configured to be less than the first frequency used for a receive operation.
26. The integrated capacitive ultrasonic transducer array and integrated circuit of claim 24 , wherein a voltage between 20 and 300 Volts is configured to be applied to the conductive ultrasonic transducer membrane during operation.
27. A method, comprising:
forming a complementary metal oxide semiconductor (CMOS) substrate having an integrated circuit therein; and
bonding an engineered substrate with the CMOS substrate, the engineered substrate comprising a conductive bottom silicon ultrasonic transducer layer positioned above the integrated circuit and further comprising a silicon membrane having a thickness between 1 micron and 10 microns integrated with the conductive bottom silicon ultrasonic transducer layer, with a plurality of ultrasonic transducer cavities between the bottom silicon ultrasonic transducer layer and the silicon membrane, wherein a first ultrasonic transducer cavity of the plurality of ultrasonic transducer cavities has an in-plane long dimension between 25 microns and 100 microns, and wherein an electrical contact is on the silicon membrane.
28. The method of claim 27 , wherein the bonding is performed at a temperature below 450 degrees Centigrade.
29. The method of claim 27 , wherein the bonding comprises forming a metal-metal bond.