Package on package memory interface and configuration with error code correction
Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.
1. A device comprising:
processing circuitry with a first terminal and a second terminal;
error code correction (ECC) bus coupled to the first terminal of the processing circuitry;
data bus coupled to the second terminal of the processing circuitry;
an ECC physical connector having an input coupled to the ECC bus;
a multiplexer having a first input, a second input, a select input, and an output, the first input of the multiplexer coupled to the input of the ECC physical connector, and the second input of the multiplexer coupled to the data bus;
a data physical connector having an input coupled to the output of the multiplexer; and
an AND gate having an output coupled to the select input of the multiplexer.
2. The device of claim 1 wherein the device is an external memory interface EMIF2.
3. The device of claim 1 wherein:
the device further comprises a memory having an input; and
the data physical connector has an output that is coupled to the input of the memory.
4. The device of claim 3 wherein the memory is connected as a package-on-package configuration.