Integrated circuit structures having partitioned source or drain contact structures
Integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. For example, an integrated circuit structure includes a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. A conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures. The conductive contact structure has a first portion partitioned from a second portion.
1. An integrated circuit structure, comprising:
a fin;
a gate stack over the fin;
a first epitaxial source or drain structure at a first end of the fin;
a second epitaxial source or drain structure at a second end of the fin;
a conductive contact structure coupled to one of the first or the second epitaxial source or drain structures, the conductive contact structure having a first portion partitioned from a second portion with an interface between the first portion and the second portion, wherein an entirety of the first portion is above an entirety of the second portion, and wherein the interface is below a bottommost surface of the one of the first or the second epitaxial source or drain structures.
2. The integrated circuit structure of claim 1 , wherein the first portion of the conductive contact structure is on a first surface of the one of the first or the second epitaxial source or drain structures, and the second portion of the conductive contact structure is on a second surface of the one of the first or the second epitaxial source or drain structures, the second surface opposite the first surface.
3. The integrated circuit structure of claim 1 , wherein the first portion of the conductive contact structure is in contact with the second portion of the conductive contact structure.
4. The integrated circuit structure of claim 1 , further comprising a backside interconnect on the second portion of the conductive contact structure.
5. The integrated circuit structure of claim 1 , wherein the second portion of the conductive contact structure has a bottom surface co-planar with a bottom surface of the fin.
6. The integrated circuit structure of claim 1 , wherein the fin is a silicon fin.
7. The integrated circuit structure of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.
8. An integrated circuit structure, comprising:
a nanowire;
a gate stack around the nanowire;
a first epitaxial source or drain structure at a first end of the nanowire;
a second epitaxial source or drain structure at a second end of the nanowire;
a conductive contact structure coupled to one of the first or the second epitaxial source or drain structures, the conductive contact structure having a first portion partitioned from a second portion with an interface between the first portion and the second portion, wherein an entirety of the first portion is above an entirety of the second portion, and wherein the interface is below a bottommost surface of the one of the first or the second epitaxial source or drain structures.
9. The integrated circuit structure of claim 8 , wherein the first portion of the conductive contact structure is on a first surface of the one of the first or the second epitaxial source or drain structures, and the second portion of the conductive contact structure is on a second surface of the one of the first or the second epitaxial source or drain structures, the second surface opposite the first surface.
10. The integrated circuit structure of claim 8 , wherein the first portion of the conductive contact structure is in contact with the second portion of the conductive contact structure.
11. The integrated circuit structure of claim 8 , further comprising a backside interconnect on the second portion of the conductive contact structure.
12. The integrated circuit structure of claim 8 , wherein the nanowire is a silicon nanowire.
13. The integrated circuit structure of claim 8 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.
14. An integrated circuit structure, comprising:
a vertical arrangement of nanowires above a fin;
a gate stack around the vertical arrangement of nanowires;
a first epitaxial source or drain structure at a first end of the vertical arrangement of nanowires;
a second epitaxial source or drain structure at a second end of the vertical arrangement of nanowires;
a conductive contact structure coupled to one of the first or the second epitaxial source or drain structures, the conductive contact structure having a first portion partitioned from a second portion with an interface between the first portion and the second portion, wherein an entirety of the first portion is above an entirety of the second portion, and wherein the interface is below a bottommost surface of the one of the first or the second epitaxial source or drain structures.
15. The integrated circuit structure of claim 14 , wherein the first portion of the conductive contact structure is on a first surface of the one of the first or the second epitaxial source or drain structures, and the second portion of the conductive contact structure is on a second surface of the one of the first or the second epitaxial source or drain structures, the second surface opposite the first surface.
16. The integrated circuit structure of claim 14 , wherein the first portion of the conductive contact structure is in contact with the second portion of the conductive contact structure.
17. The integrated circuit structure of claim 14 , further comprising a backside interconnect on the second portion of the conductive contact structure.
18. The integrated circuit structure of claim 14 , wherein the second portion of the conductive contact structure has a bottom surface co-planar with a bottom surface of the fin.
19. The integrated circuit structure of claim 14 , wherein the vertical arrangement of nanowires is a vertical arrangement of silicon nanowires, and the fin is a silicon fin.
20. The integrated circuit structure of claim 14 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.
21. The integrated circuit structure of claim 14 , wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.
22. The integrated circuit structure of claim 14 , wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures.
23. An integrated circuit structure, comprising:
a vertical arrangement of nanowires above a fin;
a gate stack around the vertical arrangement of nanowires;
a first epitaxial source or drain structure at a first end of the vertical arrangement of nanowires;
a second epitaxial source or drain structure at a second end of the vertical arrangement of nanowires;
a conductive contact structure coupled to one of the first or the second epitaxial source or drain structures, the conductive contact structure having a first portion partitioned from a second portion, wherein the second portion of the conductive contact structure has a bottom surface co-planar with a bottom surface of the fin.
24. An integrated circuit structure, comprising:
a fin;
a gate stack over the fin;
a first epitaxial source or drain structure at a first end of the fin;
a second epitaxial source or drain structure at a second end of the fin;
a conductive contact structure coupled to one of the first or the second epitaxial source or drain structures, the conductive contact structure having a first portion partitioned from a second portion with an interface between the first portion and the second portion, wherein the interface is below a bottommost surface of the one of the first or the second epitaxial source or drain structures, and wherein the second portion of the conductive contact structure has a bottom surface co-planar with a bottom surface of the fin.
25. An integrated circuit structure, comprising:
a vertical arrangement of nanowires above a fin;
a gate stack around the vertical arrangement of nanowires;
a first epitaxial source or drain structure at a first end of the vertical arrangement of nanowires;
a second epitaxial source or drain structure at a second end of the vertical arrangement of nanowires;
a conductive contact structure coupled to one of the first or the second epitaxial source or drain structures, the conductive contact structure having a first portion partitioned from a second portion with an interface between the first portion and the second portion, wherein the interface is below a bottommost surface of the one of the first or the second epitaxial source or drain structures, and wherein the second portion of the conductive contact structure has a bottom surface co-planar with a bottom surface of the fin.