IP Library › Granted Patent US 10,784,151
Granted Patent B2
US 10,784,151 · App. 16/128,031 · Granted Sep 22, 2020

Interconnect structure and manufacturing method for the same

Inventors: Hsiang-Wei Liu (Tainan, TW); Wei-Chen Chu (Taichung, TW); Chia-Tien Wu (Taichung, TW); Tai-I Yang (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H01L21/76807H01L21/31111H01L21/31144H01L21/76832H01L21/76834H01L21/76871H01L21/76877H01L23/5226H01L23/5283H01L23/5329H01L21/0276H01L21/31116
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Quick Facts
Patent No.
US 10,784,151
App. No.
16/128,031
Granted
Sep 22, 2020
Kind
B2
Abstract

The present disclosure provides a method for forming an interconnect structure, including forming an N th metal line principally extending in a first direction, forming a sacrificial bilayer over the N th metal line, forming a dielectric layer over the sacrificial bilayer, removing a portion of the sacrificial bilayer, forming a conductive post in the sacrificial bilayer, wherein the conductive post having a top pattern coplanar with a top surface of the sacrificial bilayer and a bottom pattern in contact with a top surface of the N th metal line, and forming an N th metal via over the sacrificial bilayer.

Claims (44)

1. A method for forming an interconnect structure, comprising:

forming an N th metal line principally extending in a first direction;

forming a sacrificial bilayer over the N th metal line, wherein the sacrificial bilayer comprises a first sacrificial layer and a second sacrificial layer over the first sacrificial layer;

removing a portion of the second sacrificial layer to expose a top surface of the first sacrificial layer;

forming a dielectric layer over a top surface of the second sacrificial layer and the top surface of the first sacrificial layer exposed from the second sacrificial layer;

removing a portion of the first sacrificial layer from the top surface exposed from the second sacrificial layer subsequent to forming the dielectric layer;

forming a conductive post in the sacrificial bilayer; and

forming an N th metal via over the sacrificial bilayer and laterally surrounded by the dielectric layer.

2. The method of claim 1 , further comprising forming an (N+1) th metal line over the N th metal via, wherein (N+1) th metal line principally extending in a second direction orthogonal to the first direction.

3. The method of claim 1 , further comprising removing a lower portion and an upper portion of the dielectric layer over the N th metal line prior to the removing the portion of the first sacrificial layer, wherein the upper portion of the dielectric layer has a width greater than a width of the lower portion of the dielectric layer.

4. The method of claim 1 , wherein the removing the portion of the second sacrificial layer comprises performing an etching operation stopping at the first sacrificial layer.

5. The method of claim 1 , further comprising forming a seed layer conforming to a sidewall of the removed portion of the sacrificial bilayer.

6. The method of claim 1 , wherein the removing the portion of the second sacrificial layer comprises patterning with a first mask.

7. The method of claim 1 , wherein the removing the portion of the first sacrificial layer comprises performing a selective wet etching operation.

8. The method of claim 1 , further comprising forming an anti-reflective layer over the sacrificial bilayer prior to removing the portion of the second sacrificial layer.

9. A method for forming an interconnect structure, comprising:

forming an N th metal line principally extending in a first direction;

forming a sacrificial bilayer above the N th metal line;

removing a portion of a second sacrificial layer of the sacrificial bilayer by patterning with a first mask;

forming a dielectric layer above the sacrificial bilayer;

removing a lower portion of the dielectric layer over the N th metal line with the first mask;

removing an upper portion of the dielectric layer over the N th metal line; and

removing a portion of a first sacrificial layer of the sacrificial bilayer by a wet etch operation, wherein the first sacrificial layer is closer to the N th metal line than the second sacrificial layer;

forming a conductive post in the sacrificial bilayer; and

forming an N th metal via over the conductive post and the sacrificial bilayer.

10. The method of claim 9 , wherein the removing the portion of the second sacrificial layer comprises performing an etching operation stopping at the first sacrificial layer.

11. The method of claim 9 , further comprising forming a seed layer in the sacrificial bilayer prior to forming the conductive post.

12. The method of claim 9 , wherein removing the upper portion of the dielectric layer comprises a second mask different from the first mask.

13. The method of claim 9 , further comprising forming an (N+1) th metal line above the N th metal via, wherein (N+1) th metal line the principally extending in a second direction orthogonal to the first direction.

14. A method for forming an interconnect structure, comprising:

forming an N th metal line principally extending in a first direction, wherein N is an integer greater than or equal to 1;

forming a sacrificial bilayer over the N th metal line, wherein the sacrificial bilayer comprises a first sacrificial layer and a second sacrificial layer over the first sacrificial layer;

performing an etching operation to remove a portion of the second sacrificial layer, wherein the etching operation stops at the first sacrificial layer, and a sidewall of the second sacrificial layer is exposed;

forming a dielectric layer over the second sacrificial layer subsequent to the etching operation;

removing a portion of the first sacrificial layer to expose a sidewall of the first sacrificial layer and a top surface of the N th metal line subsequent to forming the dielectric layer; and

depositing a conductive material over the exposed top surface of the N th metal line, wherein the conductive material is laterally surrounded by the dielectric layer.

15. The method of claim 14 , further comprising:

removing a lower portion of the dielectric layer with a first mask; and

removing an upper portion of the dielectric layer with a second mask different from the first mask.

16. The method of claim 14 , further comprising forming a seed layer conformed to the sidewall of the first sacrificial layer and the sidewall of the second sacrificial layer.

17. The method of claim 14 , wherein the first sacrificial layer comprises metal oxides or metal oxynitrides.

18. The method of claim 14 , wherein the second sacrificial layer comprises at least one of the silicon nitride, silicon carbon nitride, silicon oxycarbide, and ornithine decarboxylase.

19. The method of claim 14 , further comprising forming an (N+1) th metal line over the N th metal line, principally extending in a second direction orthogonal to the first direction.

20. The method of claim 14 , further comprising forming an anti-reflective layer over the sacrificial bilayer prior to the etching operation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2018
From: LIU, HSIANG-WEI; CHU, WEI-CHEN; WU, CHIA-TIEN; YANG, TAI-I
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Reel/Frame 046842/0914 →
Continuity (1)
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