Apparatuses, devices and methods for sensing a snapback event in a circuit
Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.
1. A method, comprising:
applying a plurality of voltage levels to a memory cell;
determining whether a snapback event at the memory cell has occurred based at least in part on sensing a voltage level of the memory cell at one of the plurality of voltage levels;
generating one or more feedback signals based at least in part on an occurrence of the snapback event; and
disconnecting the plurality of voltage levels from the memory cell based at least in part on the one or more feedback signals.
2. The method of claim 1 , further comprising:
determining a state of the memory cell based at least in part on a comparison of the snapback event and one or more other snapback events at the memory cell.
3. The method of claim 1 , further comprising:
differentiating between a plurality of snapback events based at least in part on sensing the voltage level, wherein a state of the memory cell is determined based at least in part on the differentiating.
4. The method of claim 1 , further comprising:
sensing that the voltage level exceeds a threshold voltage level; and
generating the one or more feedback signals based at least in part on sensing that the voltage level exceeds the threshold voltage level.
5. The method of claim 1 , further comprising:
selecting the plurality of voltage levels to be applied to the memory cell before determining whether the snapback event at the memory cell has occurred.
6. The method of claim 1 , further comprising:
setting a threshold voltage level for the snapback event; and
determining whether the snapback event at the memory cell has occurred based at least in part on the threshold voltage level.
7. The method of claim 6 , wherein determining whether the snapback event at the memory cell has occurred comprises:
sensing that the voltage level of the memory cell exceeds the threshold voltage level.
8. The method of claim 1 , wherein the plurality of voltage levels are disconnected after a period of time has passed since determining whether the snapback event at the memory cell has occurred.
9. The method of claim 1 , further comprising:
applying a voltage level of the plurality of voltage levels for an amount of time based at least in part on the one or more feedback signals.
10. A device, comprising:
a memory cell;
an electric potential source coupled with the memory cell and configured to apply a plurality of voltage levels; and
a sense circuit coupled with the memory cell and configured to:
determine a state of the memory cell based at least in part on an occurrence of a snapback event at the memory cell at one of the plurality of voltage levels; and
generate one or more feedback signals based at least in part on the occurrence of the snapback event at the memory cell,
wherein the electric potential source receives the one or more feedback signals and adjusts an application of the plurality of voltage levels based at least in part on receiving the one or more feedback signals.
11. The device of claim 10 , wherein the sense circuit is further to:
determine a voltage level of the plurality of voltage levels of the memory cell; and
initiate a change in the state of the memory cell based at least in part on the voltage level.
12. The device of claim 10 , wherein the sense circuit is further to:
determine a voltage level of the plurality of voltage levels of the memory cell; and
initiate a change in a voltage level of the plurality of voltage levels applied to the memory cell based at least in part on the voltage level.
13. The device of claim 12 , wherein the sense circuit is further to:
reduce an electric potential applied to the memory cell based at least in part on the one or more feedback signals.
14. The device of claim 10 , wherein the sense circuit is further to:
disconnect an electric potential applied to the memory cell.
15. An apparatus comprising:
a memory array comprising a memory cell;
a memory controller in electronic communication with the memory array and configured to:
apply a plurality of voltage levels to the memory cell;
determine an occurrence of a snapback event at the memory cell based at least in part on sensing a voltage level of the memory cell at one of the plurality of voltage levels;
generate one or more feedback signals based at least in part on the occurrence of the snapback event; and
disconnect the plurality of voltage levels from the memory cell based at least in part on the one or more feedback signals.
16. The apparatus of claim 15 , wherein the memory controller is further configured to:
differentiate between a plurality of snapback events at the memory cell; and
determine a state of the memory cell based at least in part on differentiating between the plurality of snapback events.
17. The apparatus of claim 15 , wherein the memory controller is further configured to:
apply a voltage level of the plurality of voltage levels for an amount of time based at least in part on the one or more feedback signals.
18. The apparatus of claim 15 , wherein the memory controller is further configured to:
stop generation of an electric potential applied to the memory cell.
19. The method of claim 1 , wherein disconnecting the plurality of voltage levels from the memory cell comprises disconnecting a first node of the memory cell from an electric potential source and a second node of the memory cell from a sense circuit.
20. The apparatus of claim 15 , wherein the memory controller is configured to disconnect the plurality of voltage levels applied to the memory cell by disconnecting a first node of the memory cell from an electric potential source and a second node of the memory cell from a sense circuit.