Imaging systems with sub-radix-2 charge sharing successive approximation register (SAR) analog-to-digital converters
View Patent ↗An image sensor may contain an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a column line which is used to read out imaging signals from the pixels. The column line may be coupled to an analog-to-digital converter for converting analog imaging signals from the pixels to digital signals. The analog-to-digital converter may be implemented as a charge sharing successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a comparator coupled to a feedback digital-to-analog converter (DAC). The comparator may have a non-zero comparator offset. The feedback DAC may include capacitors that are scaled using a sub-radix-2 sizing scheme to help improve tolerance to the comparator offset while enabling resolutions of up to 10-bits or more.
1. An image sensor, comprising:
a plurality of image sensor pixels;
an output line coupled to the plurality of image sensor pixels; and
a data converter configured to receive signals from the output line, wherein the data converter comprises:
a comparator having a comparator offset; and
a digital-to-analog converter (DAC) configured to output signals that are received by the comparator, wherein the DAC comprises capacitors sized using a sub-radix-2 scaling scheme, and wherein the sub-radix-2 scaling scheme provides a redundancy margin for improving tolerance to the comparator offset.
2. The image sensor of claim 1 , wherein the data converter comprises a successive approximation register (SAR) analog-to-digital converter (ADC).
3. The image sensor of claim 2 , wherein the data converter comprises a charge sharing SAR ADC.
4. The image sensor of claim 3 , wherein the capacitors in the DAC are all pre-charged to a known reference voltage level.
5. The image sensor of claim 3 , wherein the charge sharing SAR ADC has a resolution that exceeds 8 bits.
6. The image sensor of claim 3 , wherein the charge sharing SAR ADC has at least 10 bits of resolution.
7. The image sensor of claim 3 , wherein the sub-radix-2 scaling scheme has a scaling factor ranging from 1.5 to 1.9999.
8. The image sensor of claim 3 , wherein the capacitors in the DAC comprise a first set of capacitors sized using a first sub-radix-2 scaling factor and a second set of capacitors sized using a second scaling factor that is different than the first sub-radix-2 scaling factor.
9. The image sensor of claim 8 , wherein the second scaling factor is complementary to the first sub-radix-2 scaling factor.
10. The image sensor of claim 3 , wherein the comparator is calibrated to reduce the comparator offset.
11. The image sensor of claim 3 , wherein the capacitors in the DAC have corresponding digital weights, and wherein the digital weights of the capacitors in the DAC are calibrated.
12. An image sensor, comprising:
a plurality of imaging pixels;
a column line coupled to the plurality of imaging pixels; and
a charge sharing successive approximation register (SAR) analog-to-digital converter (ADC) with at least 9 bits of resolution.
13. The image sensor of claim 12 , wherein the charge sharing SAR ADC is implemented using a sub-radix-2 capacitor scaling scheme.
14. The image sensor of claim 12 , wherein the SAR ADC comprises a comparator with a comparator offset, and wherein the sub-radix-2 capacitor scaling scheme provides a margin to mitigate the comparator offset without affecting the resolution of the SAR ADC.
15. The image sensor of claim 12 , wherein the sub-radix-2 capacitor scaling scheme uses a first scaling factor that is less than 2, and a second scaling factor that is complementary to the first scaling factor.
16. The image sensor of claim 14 , wherein the comparator is calibrated to reduce the comparator offset.
17. A data converter, comprising:
a comparator configured to receive an input signal, wherein the comparator exhibits a comparator offset;
a digital-to-analog converter (DAC) configured to generate an analog signal, wherein the comparator is further configured to compare the input signal against the analog signal; and
control logic configured to receive signals from the comparator and output signals to the DAC, wherein the DAC includes parallel capacitors that are sized in a way to provide redundancy for compensating the comparator offset.
18. The data converter of claim 17 , wherein the data converter is a charge sharing successive approximation register (SAR) analog-to-digital converter (ADC).
19. The data converter of claim 18 , wherein the SAR ADC has at least 10 bits of resolution.
20. The data converter of claim 19 , wherein the comparator is calibrated to reduce the comparator offset.
21. The data converter of claim 20 , wherein the parallel capacitors have weights that are digitally calibrated.
22. The data converter of claim 18 , wherein at least some of the parallel capacitors are scaled using a first factor less than 2.
23. The data converter of claim 18 , wherein a first subset of the parallel capacitors are scaled using a first factor less than 2, and wherein a second subset of the parallel capacitors are scaled using a second factor ranging from 1.5 to 2.