Interleaving switch cap integrator DAC for low noise ramp generation with lower AVDD power supply
Disclosure relates to interleaving switch cap integrator DAC for low noise ramp generation with lower AVDD power supply. Embodiments of interleaving switch cap integrator digital-to-analog converter (DAC) for low noise ramp generation while operating with low power supply voltage are described. In one embodiment, an image sensor includes: a plurality of pixels arranged in rows and columns of a pixel array; a bitline electrically coupled to an active pixel; and a switched capacitor current digital to analog converter (IDAC) coupled to the bitline. The IDAC includes a plurality of switch banks, where each switch bank is configured to receive a control signal for controlling opening and closing of switches of the switch bank. The control signals are offset in time. An integrator is coupled to the plurality of switch banks. The integrator is configured for generating an output signal based on input signals received from the plurality of switch banks.
1 . An image sensor, comprising:
a plurality of pixels arranged in rows and columns of a pixel array;
a bitline electrically coupled to a pixel; and
a switched capacitor current digital to analog converter (IDAC) coupled to the bitline, the IDAC comprising:
a plurality of switch banks, each switch bank configured to receive a control signal for controlling opening and closing of switches of the switch bank, wherein control signals are offset in time; and
an integrator coupled to the plurality of switch banks, wherein the integrator is configured for generating an output signal based on input signals received from the plurality of switch banks,
wherein a time offset between the control signals for two switch banks of the plurality of switch banks satisfies:
Δ
T
=
T
/
N
,
where T is a period of the control signal, and N is a number of switch banks of the plurality of switch banks.
2 . The image sensor of claim 1 , wherein each switch bank is configured to generate a peak current that is offset by ΔT from a next peak current.
3 . The image sensor of claim 1 , wherein each switch bank comprises a first switch, a second switch, a third switch, and a fourth switch, wherein the first switch and the second switch are controlled by a first control signal, wherein the third switch and the fourth switch are controlled by a second control signal, and wherein a first phase of the first control signal differs by π from a second phase of the second control signal.
4 . The image sensor of claim 3 , wherein each switch bank comprises a channel sample capacitor.
5 . The image sensor of claim 4 , wherein the integrator comprises:
an op-amp; and
an integrator capacitor.
6 . The image sensor of claim 5 , wherein each switch bank comprises a first buffer coupled to the first switch, a second buffer coupled to the second switch, and a third buffer coupled between an inverting input and a non-inverting input of the op-amp,
wherein each first buffer is configured for providing a first differential voltage reference Vref1 to the first switch, each second buffer is configured for providing a second differential voltage references Vref2 to the second switch, and wherein the voltage references Vref1 and Vref2 are configured for charging the channel sample capacitor.
7 . The image sensor of claim 5 , wherein a capacitance of the integrator capacitor is an order of magnitude greater than a capacitance of the channel sample capacitor.
8 . The image sensor of claim 4 , wherein the channel sample capacitor is a Metal-Oxide-Metal (MOM) interdigitated capacitor.
9 . The image sensor of claim 8 , wherein the channel sample capacitor comprises:
a first plate and a second plate that are interdigitated in a first metal layer; and
an electrical connection between the first plate of the channel sample capacitor and the second metal layer.
10 . A method of a correlated double sampling (CDS) readout of an image sensor having a plurality of pixels of a pixel array, the method comprising:
exposing a pixel to light;
coupling the pixel to a bitline through a select transistor (SEL);
generating a ramp voltage by a switched capacitor current digital to analog converter (IDAC) coupled to the bitline, wherein generating the ramp voltage comprises:
controlling opening and closing of switches of a plurality of switch banks by control signals, wherein each switch bank is configured for receiving a control signal, and wherein the control signals are offset in time; and
receiving, by an integrator, a plurality of current inputs generated by the plurality of switch banks; and
generating an output signal by the integrator; and
determining at least one comparator flip by finding an intersection between the ramp voltage and a pixel voltage from the pixel,
wherein a time offset between the control signals for two switch banks of the plurality of switch banks satisfies:
Δ
T
=
T
/
N
,
where T is a period of the control signal, and N is a number of switch banks of the plurality of switch banks.
11 . The method of claim 10 , further comprising generating, by each switch bank, a peak current that is offset by ΔT from a next peak current.
12 . The method of claim 10 , wherein each switch bank comprises a first switch, a second switch, a third switch, and a fourth switch, the method further comprising:
controlling the first switch and the second switch by a first control signal; and
controlling the third switch and the fourth switch by a second control signal,
wherein a first phase of the first control signal differs by π from a second phase of the second control signal.
13 . The method of claim 12 , wherein each switch bank comprises a channel sample capacitor.
14 . The method of claim 13 , wherein each switch bank comprises a first buffer coupled to the first switch, and a second buffer coupled to the second switch, the method further comprising:
providing a first differential voltage reference Vref1 to the first switch of each switch bank;
providing a second differential voltage references Vref2 to the second switch of each switch bank; and
charging the channel sample capacitor by the voltage references Vref1 and Vref2.
15 . The method of claim 13 , wherein the integrator comprises:
an op-amp; and
an integrator capacitor.
16 . The method of claim 15 , wherein each switch bank comprises a third buffer coupled between an inverting input and a non-inverting input of an op-amp of the integrator.
17 . The image sensor of claim 15 , wherein a capacitance of the integrator capacitor is an order of magnitude greater than a capacitance of the channel sample capacitor.
18 . The method of claim 13 , wherein the channel sample capacitor is a Metal-Oxide-Metal (MOM) interdigitated capacitor.
19 . The image sensor of claim 18 , wherein the channel sample capacitor comprises a first plate and a second plate that are interdigitated in a first metal layer, and an electrical connection between the first plate of the channel sample capacitor and the second metal layer.