Electrically testable integrated circuit packaging
An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.
1. An integrated circuit packaging structure, including:
(1) a thin-film tile having a first surface and a second surface, and provisioned with probe-compatible connection pads on at least one of the first surface and/or the second surface; and
(2) a plurality of integrated circuit dies flip-chip assembled on at least the first surface of the thin-film tile, each integrated circuit die and a corresponding portion of the thin-film tile forming a die/tile assembly testable at microwave frequencies;
wherein the probe-compatible connection pads on at least one of the first surface and/or the second surface of the thin-film tile are accessible for connection to one or more probes after assembly of the plurality of flip-chipped integrated circuit dies on the thin-film tile, and the thin-film tile is configured to allow testing, before singulation of the die/tile assemblies, of some or all of the integrated circuit dies flip-chip assembled on at least the first surface of the thin-film tile.
2. The invention of claim 1 , wherein at least one of the plurality of integrated circuit dies has a different functionality and/or size from at least one other of the plurality of integrated circuit dies.
3. The invention of claim 1 , wherein at least some of the probe-compatible connection pads are configured as ground-signal-ground sets of pads.
4. The invention of claim 1 , wherein the plurality of integrated circuit dies include at least one of the following dies: RF front end chip comprising amplifiers and switches; an RF transceiver chip with up/down converters and IF amplifiers; a power control chip; and a digital/analog chip performing control and baseband functions.
5. The invention of claim 1 , wherein one or more passive devices is embedded in, formed on, and/or affixed to the thin-film tile.
6. The invention of claim 1 , further including at last one patch antenna formed on or affixed to at least one of the first surface and/or the second surface of the thin-film tile.
7. The invention of claim 1 , wherein at least one die/tile assembly further includes a battery.
8. The invention of claim 1 , wherein only a subset of probe-compatible connection pads is used for testing.
9. The invention of claim 1 , wherein each die/tile assembly is configured to be thermally coupled to a heat source or sink when at least one probe makes contact with one of the probe-compatible connection pads.
10. The invention of claim 1 , wherein two or more flip-chipped integrated circuit dies of a single die/tile assembly are interconnected by a signal path having an impedance greater than the characteristic input impedance of the one or more probes.
11. An integrated circuit packaging structure including:
(a) an electronic circuit embodied in a plurality of integrated circuit dies on a silicon-based substrate;
(b) electrically conductive structures positioned on each integrated circuit die; and
(c) a thin-film tile having a first surface and a second surface, and provisioned with probe-compatible connection pads on at least one of the first surface and/or the second surface and a plurality of vias within the tile;
where the plurality of integrated circuit dies are affixed on at least the first surface of the thin-film tile by means of the electrically conductive structures, each integrated circuit die and a corresponding portion of the thin-film tile forming a die/tile assembly testable at microwave frequencies;
wherein the probe-compatible connection pads on at least one of the first surface and/or the second surface of the thin-film tile are accessible for connection to probes after assembly of the plurality of integrated circuit dies on the thin-film tile, and the thin-film tile is configured to allow testing, before singulation of the die/tile assemblies, of some or all of the integrated circuit dies affixed on at least the first surface of the thin-film tile.
12. The invention of claim 11 , wherein at least one of the plurality of integrated circuit dies has a different functionality and/or size from at least one other of the plurality of integrated circuit dies.
13. The invention of claim 11 , wherein at least some of the probe-compatible connection pads are configured as ground-signal-ground sets of pads.
14. The invention of claim 11 , wherein the plurality of integrated circuit dies include at least one of the following dies: RF front end chip comprising amplifiers and switches; an RF transceiver chip with up/down converters and IF amplifiers; a power control chip; and a digital/analog chip performing control and baseband functions.
15. The invention of claim 11 , wherein one or more passive devices is embedded in, formed on, and/or affixed to the thin-film tile.
16. The invention of claim 11 , further including at last one patch antenna formed on or affixed to at least one of the first surface and/or the second surface of the thin-film tile.
17. The invention of claim 11 , wherein at least one die/tile assembly further includes a battery.
18. The invention of claim 11 , wherein only a subset of probe-compatible connection pads is used for testing.
19. The invention of claim 11 , wherein each die/tile assembly is configured to be thermally coupled to a heat source or sink when at least one probe makes contact with one of the probe-compatible connection pads.
20. The invention of claim 11 , wherein two or more integrated circuit dies of a single die/tile assembly are interconnected by a signal path having an impedance greater than the characteristic input impedance of the one or more probes.