Methods, apparatus, and system for metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic discharge (ESD) protection

1. A semiconductor device, comprising:

a semiconductor substrate;

a field-effect transistor (FET) comprising a gate disposed on the semiconductor substrate, a source disposed on or in the semiconductor substrate, and a drain disposed on or in the semiconductor substrate, wherein the gate, the source, and the drain extend parallel to each other in a first horizontal direction;

at least one electrostatic discharge (ESD) protection circuit in electrical contact with the source or the drain at a first location, and extending vertically and in a second horizontal direction perpendicular to the first horizontal direction to a position above a second location, wherein the second location is on the other of the source or the drain; and

a source or drain terminal disposed in electrical contact with the ESD protection circuit, wherein the source or drain terminal extends in the first direction.

2. The semiconductor device of claim 1 , wherein the at least one ESD protection circuit comprises:

a contact disposed on the source or drain at the first location; and

a first ballasting resistor comprising a first conductive element and a first via, wherein the first conductive element is disposed on the contact and the first via is disposed on the first conductive element at a position above the second location.

3. The semiconductor device of claim 2 , wherein the at least one ESD protection circuit comprises at least one additional ballasting resistor disposed vertically above the first ballasting resistor, wherein all the ballasting resistors of the ESD protection circuit comprise a vertical meander.

4. The semiconductor device of claim 3 , wherein the at least one ESD protection circuit comprises at least three ballasting resistors.

5. The semiconductor device of claim 1 , wherein the semiconductor device comprises at least one ESD protection circuit in electrical contact with the source and at least one ESD protection circuit in electrical contact with the drain.

6. The semiconductor device of claim 1 , wherein at least one of the source and the drain comprises silicide.

7. A method, comprising:

forming a field-effect transistor (FET) comprising a gate disposed on a semiconductor substrate, a source disposed on or in the semiconductor substrate, and a drain disposed on or in the semiconductor substrate, wherein the gate, the source, and the drain extend parallel to each other in a first direction;

forming at least one electrostatic discharge (ESD) protection circuit in electrical contact with the source or the drain at a first location and extending vertically and in a second horizontal direction perpendicular to the first horizontal direction to a position above a second location, wherein the second location is on the other of the source or the drain; and

forming a source or drain terminal above and in electrical contact with the ESD protection circuit, wherein the source or drain terminal extends in the first direction.

8. The method of claim 7 , wherein forming the at least one ESD protection circuit comprises:

forming a contact disposed on the source or drain at the first location; and

forming a first ballasting resistor comprising a first conductive element and a first via, wherein the first conductive element is disposed on the contact and the first via is disposed on the first conductive element at a position above the second location.

9. The method of claim 7 , wherein forming the FET comprises siliciding the source or the drain.

10. The method of claim 9 , wherein forming the FET comprises siliciding the source and siliciding the drain.

11. A system, comprising:

a process controller, configured to provide an instruction set for manufacture of a semiconductor device to a manufacturing system; and

the manufacturing system, configured to manufacture the semiconductor device according to the instruction set;

wherein the instruction set comprises instructions to:

form a field-effect transistor (FET) comprising a gate disposed on a semiconductor substrate, a source disposed on or in the semiconductor substrate, and a drain disposed on or in the semiconductor substrate, wherein the gate, the source, and the drain extend parallel to each other in a first direction;

form at least one electrostatic discharge (ESD) protection circuit in electrical contact with the source or the drain at a first location and extending vertically and in a second horizontal direction perpendicular to the first horizontal direction to a position above a second location, wherein the second location is on the other of the source or the drain; and

form a source or drain terminal above and in electrical contact with the ESD protection circuit, wherein the source or drain terminal extends in the first direction.

12. The system of claim 11 ,

wherein the instructions to form the at least one source ESD protection circuit comprise instructions to form a source contact disposed on the source at a first location; and form a first source ballasting resistor comprising a first source conductive element and a first source via, wherein the first source conductive element is disposed on the source contact and extends in a second direction perpendicular to the first direction between a position above the first location and a position above a second location, wherein the second location is on the drain, and the first source via is disposed on the first source conductive element at a position above the second location; and

wherein the instructions to form the at least one drain ESD protection circuit comprise instructions to form a drain contact disposed on the drain at a third location, wherein the third location and the second location are at different positions in the first direction; and form a first drain ballasting resistor comprising a first drain conductive element and a first drain via, wherein the first drain conductive element is disposed on the drain contact and extends in the second direction between a position above the third location and a position above a fourth location, wherein the fourth location is on the source and the first location and the fourth location are at different positions in the first direction, and the first drain via is disposed on the first drain conductive element at a position above the fourth location.

13. The system of claim 11 , wherein the instructions to form the FET comprise instructions to silicide the source, silicide the drain, or silicide both the source and the drain.

14. The system of claim 13 , wherein the instructions to form the FET comprise instructions to silicide both the source and the drain.

15. The system of claim 11 , wherein the ESD protection circuit comprises:

a contact disposed on the source or drain at the first location; and

a first ballasting resistor comprising a first conductive element and a first via, wherein the first conductive element is disposed on the contact and the first via is disposed on the first conductive element at a position above the second location.

16. The system of claim 15 , wherein the ESD protection circuit comprises at least one additional ballasting resistor disposed vertically above the first ballasting resistor, wherein all the ballasting resistors of the ESD protection circuit comprise a vertical meander.

17. The system of claim 16 , wherein the ESD protection circuit comprises at least three ballasting resistors.

18. The system of claim 15 , wherein the semiconductor device comprises at least one ESD protection circuit in electrical contact with the source and at least one ESD protection circuit in electrical contact with the drain.