IP Library Granted Patent US 10,720,511
Granted Patent B2
US 10,720,511 · App. 16/148,578 · Granted Jul 21, 2020

Trench transistors and methods with low-voltage-drop shunt to body diode

Inventors: Mohamed N. Darwish (Campbell, CA); Jun Zeng (Torrance, CA); Richard A. Blanchard (Los Altos, CA)
Assignee: MaxPower Semiconductor Inc.
H01L29/66734H01L21/26506H01L21/823412H01L21/823437H01L21/823475H01L21/823487H01L27/088H01L29/0878H01L29/1033H01L29/1095H01L29/36H01L29/407H01L29/41741H01L29/41766H01L29/4236H01L29/66727H01L29/7395H01L29/7803H01L29/7813H01L29/7827H01L29/7831H01L29/7835H01L29/0847H01L29/42368H01L29/66666
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Quick Facts
Patent No.
US 10,720,511
App. No.
16/148,578
Granted
Jul 21, 2020
Kind
B2
Abstract

Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Claims (36)

1. A power semiconductor device, comprising:

one or more first trench-gated transistors, each having a portion of a first-conductivity-type source region, and a first gate electrode which is capacitively coupled to a first body region to selectably form a first channel region therein;

one or more second trench-gated transistors, each having a portion of said first-conductivity-type source region, and a second gate electrode which is capacitively coupled to a second body region to selectably form a second channel region therein;

at least one field plate electrode separating said trench-gated transistors;

wherein said trench-gated transistors are integrated on a single semiconductor die;

wherein said second body regions are deeper than said first body regions, and said second channel regions are longer than said first channel regions; and

wherein each said first trench-gated transistor has a lower threshold voltage than each said second trench-gated transistor.

2. The device of claim 1 , wherein said first gate electrodes are shorted to said source regions.

3. The device of claim 1 , wherein said trench-gated transistors are identically electrically connected.

4. The device of claim 1 , further comprising a second-conductivity-type shield region beneath at least one said field plate electrode.

5. The device of claim 1 , further comprising a second-conductivity-type shield region beneath at least one said gate electrode.

6. The device of claim 1 , wherein at least one said gate electrode is a split gate electrode.

7. The device of claim 1 , wherein at least one said gate electrode is contained in a trench having a thick bottom oxide.

8. The device of claim 1 , wherein said first conductivity type is N type.

9. The device of claim 1 , wherein said semiconductor die is made of silicon.

10. A power semiconductor device, comprising:

one or more first trench-gated transistors, each having a portion of a first-conductivity-type source region, and a first gate electrode which is capacitively coupled to a first body region to selectably form a first channel region therein, and a drain region;

one or more second trench-gated transistors, each having another portion of said first-conductivity-type source region, and a second gate electrode which is capacitively coupled to a second body region to selectably form a second channel region therein, and a drain region;

wherein said trench-gated transistors are integrated on a single semiconductor die;

wherein said second body regions are deeper than said first body regions, and said second channel regions are longer than said first channel regions;

wherein said source regions are connected to a single common source electrode;

wherein said drain regions are connected to a single common drain electrode;

wherein said second gate electrodes are connected to a single common gate electrode; and

wherein said first gate electrodes are connected to said common source electrode.

11. The device of claim 10 , wherein each said first trench-gated transistor has a lower threshold voltage than each said second trench-gated transistor.

12. The device of claim 10 , further comprising at least one field plate electrode separating said trench-gated transistors.

13. The device of claim 12 , further comprising a second-conductivity-type shield region beneath at least one said field plate electrode.

14. The device of claim 10 , further comprising a second-conductivity-type shield region beneath at least one said gate electrode.

15. The device of claim 10 , wherein at least one said gate electrode is a split gate electrode.

16. The device of claim 10 , wherein at least one said gate electrode is contained in a trench having a thick bottom oxide.

17. The device of claim 10 , wherein said first conductivity type is N type.

18. The device of claim 10 , wherein said semiconductor die is made of silicon.

19. A power semiconductor device, comprising:

a first and second gated transistor, integrated on a single semiconductor die, both having a first-conductivity-type source region and a gate electrode which is capacitively coupled to a body region to selectably form a channel region therein;

wherein the channel region of said first gated transistor has a shorter spatial extent than does the channel region of said second gated transistor.

20. The device of claim 19 , wherein said first gated transistor has a lower threshold voltage than said second gated transistor.

Assignments (1)
SECURITY INTEREST Recorded Dec 27, 2022
From: MAXPOWER SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 062228/0648 →
Continuity (5)
Continuation 15809863 · Nov 10, 2017
Continuation 14677511 · Apr 2, 2015
Continuation 13758689 · Feb 4, 2013
Provisional Application 61597979 · Feb 13, 2012
Related Publication 20190097025A1 · Mar 28, 2019
Cited By (1)
US 12,376,319